From: Tyler Fanelli <tfanelli@redhat.com>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, mtosatti@redhat.com, armbru@redhat.com,
Tyler Fanelli <tfanelli@redhat.com>,
pbonzini@redhat.com, eblake@redhat.com
Subject: [PATCH] sev: allow capabilities to check for SEV-ES support
Date: Mon, 15 Nov 2021 14:38:04 -0500 [thread overview]
Message-ID: <20211115193804.294529-1-tfanelli@redhat.com> (raw)
Probe for SEV-ES and SEV-SNP capabilities to distinguish between Rome,
Naples, and Milan processors. Use the CPUID function to probe if a
processor is capable of running SEV-ES or SEV-SNP, rather than if it
actually is running SEV-ES or SEV-SNP.
Signed-off-by: Tyler Fanelli <tfanelli@redhat.com>
---
qapi/misc-target.json | 11 +++++++++--
target/i386/sev.c | 6 ++++--
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index 5aa2b95b7d..c3e9bce12b 100644
--- a/qapi/misc-target.json
+++ b/qapi/misc-target.json
@@ -182,13 +182,19 @@
# @reduced-phys-bits: Number of physical Address bit reduction when SEV is
# enabled
#
+# @es: SEV-ES capability of the machine.
+#
+# @snp: SEV-SNP capability of the machine.
+#
# Since: 2.12
##
{ 'struct': 'SevCapability',
'data': { 'pdh': 'str',
'cert-chain': 'str',
'cbitpos': 'int',
- 'reduced-phys-bits': 'int'},
+ 'reduced-phys-bits': 'int',
+ 'es': 'bool',
+ 'snp': 'bool'},
'if': 'TARGET_I386' }
##
@@ -205,7 +211,8 @@
#
# -> { "execute": "query-sev-capabilities" }
# <- { "return": { "pdh": "8CCDD8DDD", "cert-chain": "888CCCDDDEE",
-# "cbitpos": 47, "reduced-phys-bits": 5}}
+# "cbitpos": 47, "reduced-phys-bits": 5
+# "es": false, "snp": false}}
#
##
{ 'command': 'query-sev-capabilities', 'returns': 'SevCapability',
diff --git a/target/i386/sev.c b/target/i386/sev.c
index eede07f11d..6d78dcd744 100644
--- a/target/i386/sev.c
+++ b/target/i386/sev.c
@@ -506,7 +506,7 @@ static SevCapability *sev_get_capabilities(Error **errp)
guchar *pdh_data = NULL;
guchar *cert_chain_data = NULL;
size_t pdh_len = 0, cert_chain_len = 0;
- uint32_t ebx;
+ uint32_t eax, ebx;
int fd;
if (!kvm_enabled()) {
@@ -534,8 +534,10 @@ static SevCapability *sev_get_capabilities(Error **errp)
cap->pdh = g_base64_encode(pdh_data, pdh_len);
cap->cert_chain = g_base64_encode(cert_chain_data, cert_chain_len);
- host_cpuid(0x8000001F, 0, NULL, &ebx, NULL, NULL);
+ host_cpuid(0x8000001F, 0, &eax, &ebx, NULL, NULL);
cap->cbitpos = ebx & 0x3f;
+ cap->es = (eax & 0x8) ? true : false;
+ cap->snp = (eax & 0x10) ? true : false;
/*
* When SEV feature is enabled, we loose one bit in guest physical
--
2.31.1
next reply other threads:[~2021-11-15 19:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-15 19:38 Tyler Fanelli [this message]
2021-11-15 22:47 ` [PATCH] sev: allow capabilities to check for SEV-ES support Eric Blake
2021-11-16 9:17 ` Daniel P. Berrangé
2021-11-16 15:29 ` Tyler Fanelli
2021-11-16 15:53 ` Daniel P. Berrangé
2021-11-16 16:58 ` Tyler Fanelli
2021-11-16 17:23 ` Daniel P. Berrangé
2021-11-16 17:32 ` Tyler Fanelli
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