From: liweiwei <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, liweiwei <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com
Subject: [RFC PATCH v2 7/7] target/riscv: rvk: expose zbk* and zk* properties
Date: Tue, 16 Nov 2021 16:06:21 +0800 [thread overview]
Message-ID: <20211116080621.2521-8-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20211116080621.2521-1-liweiwei@iscas.ac.cn>
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a5ec182a86..fc7ccba672 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -661,7 +661,20 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+ DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+ DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
--
2.17.1
prev parent reply other threads:[~2021-11-16 8:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-16 8:06 [RFC PATCH v2 0/7] support subsets of scalar crypto extension liweiwei
2021-11-16 8:06 ` [RFC PATCH v2 1/7] target/riscv: rvk: add cfg properties for zbk* and zk* liweiwei
2021-11-22 1:58 ` Alistair Francis
2021-11-16 8:06 ` [RFC PATCH v2 2/7] target/riscv: rvk: add implementation of instructions for Zbk* liweiwei
2021-11-16 8:06 ` [RFC PATCH v2 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto liweiwei
2021-11-16 8:06 ` [RFC PATCH v2 4/7] target/riscv: rvk: add implementation of instructions for Zk* liweiwei
2021-11-16 8:06 ` [RFC PATCH v2 5/7] target/riscv: rvk: add CSR support for Zkr liweiwei
2021-11-16 8:06 ` [RFC PATCH v2 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions liweiwei
2021-11-16 8:06 ` liweiwei [this message]
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