From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 2/2] meson.build: Merge riscv32 and riscv64 cpu family
Date: Wed, 17 Nov 2021 19:20:31 +1000 [thread overview]
Message-ID: <20211117092031.99019-3-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211117092031.99019-1-alistair.francis@opensource.wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
In ba0e73336200, we merged riscv32 and riscv64 in configure.
However, meson does not treat them the same. We need to merge
them here as well.
Fixes: ba0e73336200
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211116095042.335224-1-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
meson.build | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/meson.build b/meson.build
index 36540e0794..e2d38a43e6 100644
--- a/meson.build
+++ b/meson.build
@@ -59,6 +59,12 @@ supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
cpu = host_machine.cpu_family()
+
+# Unify riscv* to a single family.
+if cpu in ['riscv32', 'riscv64']
+ cpu = 'riscv'
+endif
+
targetos = host_machine.system()
if cpu in ['x86', 'x86_64']
--
2.31.1
next prev parent reply other threads:[~2021-11-17 9:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-17 9:20 [PULL 0/2] riscv-to-apply queue Alistair Francis
2021-11-17 9:20 ` [PULL 1/2] target/riscv: machine: Sort the .subsections Alistair Francis
2021-11-17 9:20 ` Alistair Francis [this message]
2021-11-17 11:34 ` [PULL 0/2] riscv-to-apply queue Richard Henderson
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