qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
	alex.bennee@linaro.org, clg@kaod.org
Subject: [PATCH 31/35] target/ppc: Add helper for fmuls
Date: Fri, 19 Nov 2021 17:04:58 +0100	[thread overview]
Message-ID: <20211119160502.17432-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211119160502.17432-1-richard.henderson@linaro.org>

Use float64r32_mul.  Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/helper.h                |  1 +
 target/ppc/fpu_helper.c            | 12 ++++++++++++
 target/ppc/translate/fp-impl.c.inc | 11 ++++-------
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f72b547603..9810d416cf 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -97,6 +97,7 @@ DEF_HELPER_3(fadds, f64, env, f64, f64)
 DEF_HELPER_3(fsub, f64, env, f64, f64)
 DEF_HELPER_3(fsubs, f64, env, f64, f64)
 DEF_HELPER_3(fmul, f64, env, f64, f64)
+DEF_HELPER_3(fmuls, f64, env, f64, f64)
 DEF_HELPER_3(fdiv, f64, env, f64, f64)
 DEF_HELPER_3(fdivs, f64, env, f64, f64)
 DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4048c830e7..6278d61d36 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -533,6 +533,18 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
     return ret;
 }
 
+/* fmuls - fmuls. */
+float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2)
+{
+    float64 ret = float64r32_mul(arg1, arg2, &env->fp_status);
+    int flags = get_float_exception_flags(&env->fp_status);
+
+    if (unlikely(flags & float_flag_invalid)) {
+        float_invalid_op_mul(env, flags, 1, GETPC());
+    }
+    return ret;
+}
+
 static void float_invalid_op_div(CPUPPCState *env, int flags,
                                  bool set_fprc, uintptr_t retaddr)
 {
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 6ae556e5de..17b4d46040 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx)                                    \
 _GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type);                        \
 _GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type);
 
-#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
+#define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type)                  \
 static void gen_f##name(DisasContext *ctx)                                    \
 {                                                                             \
     TCGv_i64 t0;                                                              \
@@ -116,10 +116,7 @@ static void gen_f##name(DisasContext *ctx)                                    \
     gen_reset_fpstatus();                                                     \
     get_fpr(t0, rA(ctx->opcode));                                             \
     get_fpr(t1, rC(ctx->opcode));                                             \
-    gen_helper_f##op(t2, cpu_env, t0, t1);                                    \
-    if (isfloat) {                                                            \
-        gen_helper_frsp(t2, cpu_env, t2);                                     \
-    }                                                                         \
+    gen_helper_f##name(t2, cpu_env, t0, t1);                                  \
     set_fpr(rD(ctx->opcode), t2);                                             \
     if (set_fprf) {                                                           \
         gen_compute_fprf_float64(t2);                                         \
@@ -132,8 +129,8 @@ static void gen_f##name(DisasContext *ctx)                                    \
     tcg_temp_free_i64(t2);                                                    \
 }
 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
-_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
-_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
+_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type);                        \
+_GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type);
 
 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
 static void gen_f##name(DisasContext *ctx)                                    \
-- 
2.25.1



  parent reply	other threads:[~2021-11-19 16:31 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-19 16:04 [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups Richard Henderson
2021-11-19 16:04 ` [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 02/35] softfloat: Add flag specific to Inf - Inf Richard Henderson
2021-11-19 16:04 ` [PATCH 03/35] softfloat: Add flag specific to Inf * 0 Richard Henderson
2021-11-19 16:04 ` [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0 Richard Henderson
2021-11-19 16:04 ` [PATCH 05/35] softfloat: Add flag specific to sqrt(-x) Richard Henderson
2021-11-19 16:04 ` [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int Richard Henderson
2021-11-19 16:04 ` [PATCH 07/35] softfloat: Add flag specific to signaling nans Richard Henderson
2021-11-19 16:04 ` [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 09/35] target/ppc: Update float_invalid_op_mul " Richard Henderson
2021-11-19 16:04 ` [PATCH 10/35] target/ppc: Update float_invalid_op_div " Richard Henderson
2021-11-19 16:04 ` [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate Richard Henderson
2021-11-19 16:04 ` [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 13/35] target/ppc: Fix VXCVI return value Richard Henderson
2021-11-19 16:04 ` [PATCH 14/35] target/ppc: Remove inline from do_fri Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 16/35] target/ppc: Tidy inexact handling " Richard Henderson
2021-11-19 16:04 ` [PATCH 17/35] target/ppc: Clean up do_fri Richard Henderson
2021-11-19 16:04 ` [PATCH 18/35] target/ppc: Update fmadd for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 19/35] target/ppc: Split out do_fmadd Richard Henderson
2021-11-19 16:04 ` [PATCH 20/35] target/ppc: Do not call do_float_check_status from do_fmadd Richard Henderson
2021-11-19 16:04 ` [PATCH 21/35] target/ppc: Split out do_frsp Richard Henderson
2021-11-19 16:04 ` [PATCH 22/35] target/ppc: Update do_frsp for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 23/35] target/ppc: Use helper_todouble in do_frsp Richard Henderson
2021-11-19 16:04 ` [PATCH 24/35] target/ppc: Update sqrt for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 25/35] target/ppc: Update xsrqpi and xsrqpxp to " Richard Henderson
2021-11-19 16:04 ` [PATCH 26/35] target/ppc: Update fre " Richard Henderson
2021-11-19 16:04 ` [PATCH 27/35] softfloat: Add float64r32 arithmetic routines Richard Henderson
2021-11-19 16:04 ` [PATCH 28/35] target/ppc: Add helpers for fmadds et al Richard Henderson
2021-11-19 16:04 ` [PATCH 29/35] target/ppc: Add helper for fsqrts Richard Henderson
2021-11-19 16:04 ` [PATCH 30/35] target/ppc: Add helpers for fadds, fsubs, fdivs Richard Henderson
2021-11-19 16:04 ` Richard Henderson [this message]
2021-11-19 16:04 ` [PATCH 32/35] target/ppc: Add helper for frsqrtes Richard Henderson
2021-11-19 16:05 ` [PATCH 33/35] target/ppc: Update fres to new flags and float64r32 Richard Henderson
2021-11-19 16:05 ` [PATCH 34/35] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp Richard Henderson
2021-11-19 16:05 ` [PATCH 35/35] test/tcg/ppc64le: Add float reference files Richard Henderson
2021-11-21 17:47   ` Cédric Le Goater
2021-11-22  9:43     ` Richard Henderson
2021-11-22  9:51       ` Cédric Le Goater
2021-11-22 11:16       ` Richard Henderson
2021-11-22 13:04         ` Cédric Le Goater
2021-11-22 13:14           ` Richard Henderson
2021-11-24  9:17             ` Cédric Le Goater
2021-11-24  9:27               ` Richard Henderson
2021-11-29 14:45         ` Cédric Le Goater
2021-12-03 10:36 ` [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups Cédric Le Goater
2021-12-03 16:10 ` Matheus K. Ferst
2021-12-15 16:42 ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211119160502.17432-32-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=clg@kaod.org \
    --cc=danielhb413@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).