qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
	alex.bennee@linaro.org, clg@kaod.org
Subject: [PATCH 34/35] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
Date: Fri, 19 Nov 2021 17:05:01 +0100	[thread overview]
Message-ID: <20211119160502.17432-35-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211119160502.17432-1-richard.henderson@linaro.org>

When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only ones set within the register, and then a bitwise equality.

Fixes a bug in which a single-precision NaN is considered !SP,
because float64_eq(nan, nan) is always false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/fpu_helper.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ea238929da..b81aaca67b 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3115,26 +3115,25 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
 {
     uint32_t dcmx, sign, exp;
     uint32_t cc, match = 0, not_sp = 0;
+    float64 arg = xb->VsrD(0);
+    float64 arg_sp;
 
     dcmx = DCMX(opcode);
-    exp = (xb->VsrD(0) >> 52) & 0x7FF;
+    exp = (arg >> 52) & 0x7FF;
+    sign = float64_is_neg(arg);
 
-    sign = float64_is_neg(xb->VsrD(0));
-    if (float64_is_any_nan(xb->VsrD(0))) {
+    if (float64_is_any_nan(arg)) {
         match = extract32(dcmx, 6, 1);
-    } else if (float64_is_infinity(xb->VsrD(0))) {
+    } else if (float64_is_infinity(arg)) {
         match = extract32(dcmx, 4 + !sign, 1);
-    } else if (float64_is_zero(xb->VsrD(0))) {
+    } else if (float64_is_zero(arg)) {
         match = extract32(dcmx, 2 + !sign, 1);
-    } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
-               (exp > 0 && exp < 0x381)) {
+    } else if (float64_is_zero_or_denormal(arg) || (exp > 0 && exp < 0x381)) {
         match = extract32(dcmx, 0 + !sign, 1);
     }
 
-    not_sp = !float64_eq(xb->VsrD(0),
-                         float32_to_float64(
-                             float64_to_float32(xb->VsrD(0), &env->fp_status),
-                             &env->fp_status), &env->fp_status);
+    arg_sp = helper_todouble(helper_tosingle(arg));
+    not_sp = arg != arg_sp;
 
     cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
     env->fpscr &= ~FP_FPCC;
-- 
2.25.1



  parent reply	other threads:[~2021-11-19 16:41 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-19 16:04 [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups Richard Henderson
2021-11-19 16:04 ` [PATCH 01/35] softfloat: Extend float_exception_flags to 16 bits Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 02/35] softfloat: Add flag specific to Inf - Inf Richard Henderson
2021-11-19 16:04 ` [PATCH 03/35] softfloat: Add flag specific to Inf * 0 Richard Henderson
2021-11-19 16:04 ` [PATCH 04/35] softfloat: Add flags specific to Inf / Inf and 0 / 0 Richard Henderson
2021-11-19 16:04 ` [PATCH 05/35] softfloat: Add flag specific to sqrt(-x) Richard Henderson
2021-11-19 16:04 ` [PATCH 06/35] softfloat: Add flag specific to convert non-nan to int Richard Henderson
2021-11-19 16:04 ` [PATCH 07/35] softfloat: Add flag specific to signaling nans Richard Henderson
2021-11-19 16:04 ` [PATCH 08/35] target/ppc: Update float_invalid_op_addsub for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 09/35] target/ppc: Update float_invalid_op_mul " Richard Henderson
2021-11-19 16:04 ` [PATCH 10/35] target/ppc: Update float_invalid_op_div " Richard Henderson
2021-11-19 16:04 ` [PATCH 11/35] target/ppc: Move float_check_status from FPU_FCTI to translate Richard Henderson
2021-11-19 16:04 ` [PATCH 12/35] target/ppc: Update float_invalid_cvt for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 13/35] target/ppc: Fix VXCVI return value Richard Henderson
2021-11-19 16:04 ` [PATCH 14/35] target/ppc: Remove inline from do_fri Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 15/35] target/ppc: Use FloatRoundMode in do_fri Richard Henderson
2021-12-03 21:33   ` Philippe Mathieu-Daudé
2021-11-19 16:04 ` [PATCH 16/35] target/ppc: Tidy inexact handling " Richard Henderson
2021-11-19 16:04 ` [PATCH 17/35] target/ppc: Clean up do_fri Richard Henderson
2021-11-19 16:04 ` [PATCH 18/35] target/ppc: Update fmadd for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 19/35] target/ppc: Split out do_fmadd Richard Henderson
2021-11-19 16:04 ` [PATCH 20/35] target/ppc: Do not call do_float_check_status from do_fmadd Richard Henderson
2021-11-19 16:04 ` [PATCH 21/35] target/ppc: Split out do_frsp Richard Henderson
2021-11-19 16:04 ` [PATCH 22/35] target/ppc: Update do_frsp for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 23/35] target/ppc: Use helper_todouble in do_frsp Richard Henderson
2021-11-19 16:04 ` [PATCH 24/35] target/ppc: Update sqrt for new flags Richard Henderson
2021-11-19 16:04 ` [PATCH 25/35] target/ppc: Update xsrqpi and xsrqpxp to " Richard Henderson
2021-11-19 16:04 ` [PATCH 26/35] target/ppc: Update fre " Richard Henderson
2021-11-19 16:04 ` [PATCH 27/35] softfloat: Add float64r32 arithmetic routines Richard Henderson
2021-11-19 16:04 ` [PATCH 28/35] target/ppc: Add helpers for fmadds et al Richard Henderson
2021-11-19 16:04 ` [PATCH 29/35] target/ppc: Add helper for fsqrts Richard Henderson
2021-11-19 16:04 ` [PATCH 30/35] target/ppc: Add helpers for fadds, fsubs, fdivs Richard Henderson
2021-11-19 16:04 ` [PATCH 31/35] target/ppc: Add helper for fmuls Richard Henderson
2021-11-19 16:04 ` [PATCH 32/35] target/ppc: Add helper for frsqrtes Richard Henderson
2021-11-19 16:05 ` [PATCH 33/35] target/ppc: Update fres to new flags and float64r32 Richard Henderson
2021-11-19 16:05 ` Richard Henderson [this message]
2021-11-19 16:05 ` [PATCH 35/35] test/tcg/ppc64le: Add float reference files Richard Henderson
2021-11-21 17:47   ` Cédric Le Goater
2021-11-22  9:43     ` Richard Henderson
2021-11-22  9:51       ` Cédric Le Goater
2021-11-22 11:16       ` Richard Henderson
2021-11-22 13:04         ` Cédric Le Goater
2021-11-22 13:14           ` Richard Henderson
2021-11-24  9:17             ` Cédric Le Goater
2021-11-24  9:27               ` Richard Henderson
2021-11-29 14:45         ` Cédric Le Goater
2021-12-03 10:36 ` [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups Cédric Le Goater
2021-12-03 16:10 ` Matheus K. Ferst
2021-12-15 16:42 ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211119160502.17432-35-richard.henderson@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=clg@kaod.org \
    --cc=danielhb413@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).