From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Francisco Iglesias <francisco.iglesias@xilinx.com>
Cc: peter.maydell@linaro.org, frasse.iglesias@gmail.com,
alistair@alistair23.me, qemu-devel@nongnu.org,
alistair23@gmail.com
Subject: Re: [PATCH v2 07/10] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model
Date: Tue, 23 Nov 2021 11:45:40 +0100 [thread overview]
Message-ID: <20211123104540.GB5816@toto> (raw)
In-Reply-To: <20211123103428.8765-8-francisco.iglesias@xilinx.com>
On Tue, Nov 23, 2021 at 10:34:25AM +0000, Francisco Iglesias wrote:
> Connect the OSPI flash memory controller model (including the source and
> destination DMA).
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
> ---
> hw/arm/xlnx-versal.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/xlnx-versal.h | 20 ++++++++++
> 2 files changed, 107 insertions(+)
>
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index 08e250945f..20c82bff01 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -24,6 +24,7 @@
>
> #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
> #define GEM_REVISION 0x40070106
> +#define NUM_OSPI_IRQ_LINES 3
>
> static void versal_create_apu_cpus(Versal *s)
> {
> @@ -385,6 +386,91 @@ static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic)
> sysbus_connect_irq(sbd, 0, pic[VERSAL_PMC_IOU_SLCR_IRQ]);
> }
>
> +static void versal_create_ospi(Versal *s, qemu_irq *pic)
> +{
> + SysBusDevice *sbd;
> + MemoryRegion *mr_dac;
> +
> + memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s),
> + "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE);
> +
> + object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi,
> + TYPE_XILINX_VERSAL_OSPI);
> +
> + mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1);
> + memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac);
> +
> + /* Create the OSPI destination DMA */
> + object_initialize_child(OBJECT(s), "versal-ospi-dma-dst",
> + &s->pmc.iou.ospi.dma_dst,
> + TYPE_XLNX_CSU_DMA);
> +
> + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst),
> + "dma", OBJECT(get_system_memory()),
> + &error_abort);
> +
> + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst);
> + sysbus_realize(sbd, &error_fatal);
> +
> + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST,
> + sysbus_mmio_get_region(sbd, 0));
> +
> + /* Create the OSPI source DMA */
> + object_initialize_child(OBJECT(s), "versal-ospi-dma-src",
> + &s->pmc.iou.ospi.dma_src,
> + TYPE_XLNX_CSU_DMA);
> +
> + object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst",
> + false, &error_abort);
> +
> + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
> + "dma", OBJECT(mr_dac), &error_abort);
> +
> + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src),
> + "stream-connected-dma",
> + OBJECT(&s->pmc.iou.ospi.dma_dst),
> + &error_abort);
> +
> + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src);
> + sysbus_realize(sbd, &error_fatal);
> +
> + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC,
> + sysbus_mmio_get_region(sbd, 0));
> +
> + /* Realize the OSPI */
> + object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src",
> + OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort);
> +
> + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi);
> + sysbus_realize(sbd, &error_fatal);
> +
> + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI,
> + sysbus_mmio_get_region(sbd, 0));
> +
> + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC,
> + &s->pmc.iou.ospi.linear_mr);
> +
> + /* ospi_mux_sel */
> + qdev_connect_gpio_out(DEVICE(&s->pmc.iou.slcr), 3,
> + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.ospi), 0));
> +
> + /* OSPI irq */
> + object_initialize_child(OBJECT(s), "ospi-irq",
> + &s->pmc.iou.ospi.irq, TYPE_OR_IRQ);
> + object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq),
> + "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal);
> + qdev_realize(DEVICE(&s->pmc.iou.ospi.irq), NULL, &error_fatal);
> +
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0,
> + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 0));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0,
> + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 1));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0,
> + qdev_get_gpio_in(DEVICE(&s->pmc.iou.ospi.irq), 2));
> +
> + qdev_connect_gpio_out(DEVICE(&s->pmc.iou.ospi.irq), 0,
> + pic[VERSAL_OSPI_IRQ]);
> +}
>
> /* This takes the board allocated linear DDR memory and creates aliases
> * for each split DDR range/aperture on the Versal address map.
> @@ -477,6 +563,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
> versal_create_bbram(s, pic);
> versal_create_efuse(s, pic);
> versal_create_pmc_iou_slcr(s, pic);
> + versal_create_ospi(s, pic);
> versal_map_ddr(s);
> versal_unimp(s);
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 729c093dfc..d5c9c3900b 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -26,6 +26,8 @@
> #include "hw/misc/xlnx-versal-xramc.h"
> #include "hw/nvram/xlnx-bbram.h"
> #include "hw/nvram/xlnx-versal-efuse.h"
> +#include "hw/ssi/xlnx-versal-ospi.h"
> +#include "hw/dma/xlnx_csu_dma.h"
> #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
>
> #define TYPE_XLNX_VERSAL "xlnx-versal"
> @@ -80,6 +82,14 @@ struct Versal {
> struct {
> SDHCIState sd[XLNX_VERSAL_NR_SDS];
> XlnxVersalPmcIouSlcr slcr;
> +
> + struct {
> + XlnxVersalOspi ospi;
> + XlnxCSUDMA dma_src;
> + XlnxCSUDMA dma_dst;
> + MemoryRegion linear_mr;
> + qemu_or_irq irq;
> + } ospi;
> } iou;
>
> XlnxZynqMPRTC rtc;
> @@ -116,6 +126,7 @@ struct Versal {
> #define VERSAL_BBRAM_APB_IRQ_0 121
> #define VERSAL_RTC_APB_ERR_IRQ 121
> #define VERSAL_PMC_IOU_SLCR_IRQ 121
> +#define VERSAL_OSPI_IRQ 124
> #define VERSAL_SD0_IRQ_0 126
> #define VERSAL_EFUSE_IRQ 139
> #define VERSAL_RTC_ALARM_IRQ 142
> @@ -184,6 +195,15 @@ struct Versal {
> #define MM_PMC_PMC_IOU_SLCR 0xf1060000
> #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
>
> +#define MM_PMC_OSPI 0xf1010000
> +#define MM_PMC_OSPI_SIZE 0x10000
> +
> +#define MM_PMC_OSPI_DAC 0xc0000000
> +#define MM_PMC_OSPI_DAC_SIZE 0x20000000
> +
> +#define MM_PMC_OSPI_DMA_DST 0xf1011800
> +#define MM_PMC_OSPI_DMA_SRC 0xf1011000
> +
> #define MM_PMC_SD0 0xf1040000U
> #define MM_PMC_SD0_SIZE 0x10000
> #define MM_PMC_BBRAM_CTRL 0xf11f0000
> --
> 2.11.0
>
next prev parent reply other threads:[~2021-11-23 11:07 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-23 10:34 [PATCH v2 00/10] Xilinx Versal's PMC SLCR and OSPI support Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 01/10] hw/misc: Add a model of Versal's PMC SLCR Francisco Iglesias
2021-11-23 10:47 ` Edgar E. Iglesias
2021-11-23 10:34 ` [PATCH v2 02/10] hw/arm/xlnx-versal: Connect " Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 03/10] include/hw/dma/xlnx_csu_dma: Include ptimer.h and stream.h in the header Francisco Iglesias
2021-11-23 10:45 ` Philippe Mathieu-Daudé
2021-11-24 10:15 ` Francisco Iglesias
2021-11-23 10:47 ` Edgar E. Iglesias
2021-11-23 10:34 ` [PATCH v2 04/10] hw/dma: Add the DMA control interface Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 05/10] hw/dma/xlnx_csu_dma: Implement " Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 06/10] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 07/10] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model Francisco Iglesias
2021-11-23 10:45 ` Edgar E. Iglesias [this message]
2021-11-23 10:34 ` [PATCH v2 08/10] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g Francisco Iglesias
2021-11-23 10:34 ` [PATCH v2 09/10] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI Francisco Iglesias
2021-11-23 10:46 ` Edgar E. Iglesias
2021-11-23 10:34 ` [PATCH v2 10/10] MAINTAINERS: Add an entry for Xilinx Versal OSPI Francisco Iglesias
2021-11-23 10:46 ` Edgar E. Iglesias
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