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From: Francisco Iglesias <francisco.iglesias@xilinx.com>
To: <qemu-devel@nongnu.org>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
	frasse.iglesias@gmail.com, alistair@alistair23.me,
	alistair23@gmail.com, philmd@redhat.com
Subject: [PATCH v3 05/10] hw/dma/xlnx_csu_dma: Implement the DMA control interface
Date: Wed, 24 Nov 2021 10:15:50 +0000	[thread overview]
Message-ID: <20211124101555.1410-6-francisco.iglesias@xilinx.com> (raw)
In-Reply-To: <20211124101555.1410-1-francisco.iglesias@xilinx.com>

Implement the DMA control interface for allowing control of DMA operations
from inside models that contain instances of (and reuse) the Xilinx CSU
DMA.

Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/dma/xlnx_csu_dma.c         | 32 ++++++++++++++++++++++++++++++++
 include/hw/dma/xlnx_csu_dma.h |  4 ++++
 2 files changed, 36 insertions(+)

diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
index 896bb3574d..9ed6e82225 100644
--- a/hw/dma/xlnx_csu_dma.c
+++ b/hw/dma/xlnx_csu_dma.c
@@ -277,6 +277,11 @@ static uint32_t xlnx_csu_dma_advance(XlnxCSUDMA *s, uint32_t len)
         s->regs[R_ADDR_MSB] = dst >> 32;
     }
 
+    /* Notify dma-ctrl clients when the transfer has been completed */
+    if (size == 0 && s->dma_ctrl_notify) {
+        s->dma_ctrl_notify(s->dma_ctrl_opaque);
+    }
+
     if (size == 0) {
         xlnx_csu_dma_done(s);
     }
@@ -472,6 +477,29 @@ static uint64_t addr_msb_pre_write(RegisterInfo *reg, uint64_t val)
     return val & R_ADDR_MSB_ADDR_MSB_MASK;
 }
 
+static void xlnx_csu_dma_dma_ctrl_read(DmaCtrl *dma_ctrl, hwaddr addr,
+                                         uint32_t len, DmaCtrlNotify *notify,
+                                         bool start_dma)
+{
+    XlnxCSUDMA *s = XLNX_CSU_DMA(dma_ctrl);
+    RegisterInfo *reg = &s->regs_info[R_SIZE];
+    uint64_t we = MAKE_64BIT_MASK(0, 4 * 8);
+
+    s->regs[R_ADDR] = addr;
+    s->regs[R_ADDR_MSB] = (uint64_t)addr >> 32;
+
+    if (notify) {
+        s->dma_ctrl_notify = notify->cb;
+        s->dma_ctrl_opaque = notify->opaque;
+    }
+
+    if (start_dma) {
+        register_write(reg, len, we, object_get_typename(OBJECT(s)), false);
+    } else {
+        s->regs[R_SIZE] = len;
+    }
+}
+
 static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] = {
 #define DMACH_REGINFO(NAME, snd)                                              \
     (const RegisterAccessInfo []) {                                           \
@@ -696,6 +724,7 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
+    DmaCtrlClass *dcc = DMA_CTRL_CLASS(klass);
 
     dc->reset = xlnx_csu_dma_reset;
     dc->realize = xlnx_csu_dma_realize;
@@ -704,6 +733,8 @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data)
 
     ssc->push = xlnx_csu_dma_stream_push;
     ssc->can_push = xlnx_csu_dma_stream_can_push;
+
+    dcc->read = xlnx_csu_dma_dma_ctrl_read;
 }
 
 static void xlnx_csu_dma_init(Object *obj)
@@ -731,6 +762,7 @@ static const TypeInfo xlnx_csu_dma_info = {
     .instance_init = xlnx_csu_dma_init,
     .interfaces = (InterfaceInfo[]) {
         { TYPE_STREAM_SINK },
+        { TYPE_DMA_CTRL },
         { }
     }
 };
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h
index 28806628b1..18cb45a024 100644
--- a/include/hw/dma/xlnx_csu_dma.h
+++ b/include/hw/dma/xlnx_csu_dma.h
@@ -25,6 +25,7 @@
 #include "hw/register.h"
 #include "hw/ptimer.h"
 #include "hw/stream.h"
+#include "hw/dma/dma-ctrl.h"
 
 #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma"
 
@@ -47,6 +48,9 @@ typedef struct XlnxCSUDMA {
     StreamCanPushNotifyFn notify;
     void *notify_opaque;
 
+    dmactrl_notify_fn dma_ctrl_notify;
+    void *dma_ctrl_opaque;
+
     uint32_t regs[XLNX_CSU_DMA_R_MAX];
     RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX];
 } XlnxCSUDMA;
-- 
2.11.0



  parent reply	other threads:[~2021-11-24 10:33 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-24 10:15 [PATCH v3 00/10] Xilinx Versal's PMC SLCR and OSPI support Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 01/10] hw/misc: Add a model of Versal's PMC SLCR Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 02/10] hw/arm/xlnx-versal: Connect " Francisco Iglesias
2021-11-29 17:32   ` Peter Maydell
2021-11-24 10:15 ` [PATCH v3 03/10] include/hw/dma/xlnx_csu_dma: Add in missing includes in the header Francisco Iglesias
2021-11-29 17:32   ` Peter Maydell
2021-11-24 10:15 ` [PATCH v3 04/10] hw/dma: Add the DMA control interface Francisco Iglesias
2021-11-29 17:44   ` Peter Maydell
2021-12-01 15:40     ` Francisco Iglesias
2021-11-24 10:15 ` Francisco Iglesias [this message]
2021-11-24 10:15 ` [PATCH v3 06/10] hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 07/10] hw/arm/xlnx-versal: Connect the OSPI flash memory controller model Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 08/10] hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 09/10] hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI Francisco Iglesias
2021-11-24 10:15 ` [PATCH v3 10/10] MAINTAINERS: Add an entry for Xilinx Versal OSPI Francisco Iglesias

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