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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t17sm18810912wmq.15.2021.11.29.02.39.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Nov 2021 02:39:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 0/5] target-arm queue Date: Mon, 29 Nov 2021 10:39:10 +0000 Message-Id: <20211129103915.1162989-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi; this is a collection of mostly GIC related patches for rc3. The "Update cached state after LPI state changes" fix is important and fixes what would otherwise be a regression since we enable the ITS by default in the virt board now. The others are not regressions but I think are OK for rc3 as they're fairly self contained (and two of them are fixes to new-in-6.2 functionality). thanks -- PMM The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a: Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129 for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9: hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000) ---------------------------------------------------------------- target-arm queue: * virt: Diagnose attempts to enable MTE or virt when using HVF accelerator * GICv3 ITS: Allow clearing of ITS CTLR Enabled bit * GICv3: Update cached state after LPI state changes * GICv3: Fix handling of LPIs in list registers ---------------------------------------------------------------- Alexander Graf (1): hw/arm/virt: Extend nested and mte checks to hvf Peter Maydell (3): hw/intc/arm_gicv3: Update cached state after LPI state changes hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function hw/intc/arm_gicv3: fix handling of LPIs in list registers Shashi Mallela (1): hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++ hw/arm/virt.c | 15 +++++++++------ hw/intc/arm_gicv3.c | 6 ++++-- hw/intc/arm_gicv3_cpuif.c | 9 ++++----- hw/intc/arm_gicv3_its.c | 7 ++++--- hw/intc/arm_gicv3_redist.c | 14 ++++++++++---- 6 files changed, 61 insertions(+), 20 deletions(-)