From: David Woodhouse <dwmw2@infradead.org>
To: qemu-devel@nongnu.org
Cc: Eduardo Habkost <eduardo@habkost.net>,
kvm@vger.kernel.org, "Michael S. Tsirkin" <mst@redhat.com>,
Jason Wang <jasowang@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Peter Xu <peterx@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>
Subject: [PATCH v2 3/4] intel_iommu: Only allow interrupt remapping to be enabled if it's supported
Date: Thu, 9 Dec 2021 22:08:39 +0000 [thread overview]
Message-ID: <20211209220840.14889-3-dwmw2@infradead.org> (raw)
In-Reply-To: <20211209220840.14889-1-dwmw2@infradead.org>
From: David Woodhouse <dwmw@amazon.co.uk>
We should probably check if we were meant to be exposing IR, before
letting the guest turn the IRE bit on.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Peter Xu <peterx@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
---
hw/i386/intel_iommu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 9a3cb2b789..bd288d45bb 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2197,6 +2197,7 @@ static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
/* Handle write to Global Command Register */
static void vtd_handle_gcmd_write(IntelIOMMUState *s)
{
+ X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
uint32_t changed = status ^ val;
@@ -2218,7 +2219,8 @@ static void vtd_handle_gcmd_write(IntelIOMMUState *s)
/* Set/update the interrupt remapping root-table pointer */
vtd_handle_gcmd_sirtp(s);
}
- if (changed & VTD_GCMD_IRE) {
+ if ((changed & VTD_GCMD_IRE) &&
+ x86_iommu_ir_supported(x86_iommu)) {
/* Interrupt remap enable/disable */
vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
}
--
2.31.1
next prev parent reply other threads:[~2021-12-09 22:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-09 22:08 [PATCH v2 1/4] target/i386: Fix sanity check on max APIC ID / X2APIC enablement David Woodhouse
2021-12-09 22:08 ` [PATCH v2 2/4] intel_iommu: Support IR-only mode without DMA translation David Woodhouse
2021-12-16 8:47 ` Peter Xu
2021-12-09 22:08 ` David Woodhouse [this message]
2021-12-09 22:08 ` [PATCH v2 4/4] intel_iommu: Fix irqchip / X2APIC configuration checks David Woodhouse
2021-12-16 8:47 ` Peter Xu
2021-12-17 16:51 ` David Woodhouse
2021-12-20 10:07 ` Peter Xu
2021-12-16 6:29 ` [PATCH v2 1/4] target/i386: Fix sanity check on max APIC ID / X2APIC enablement Peter Xu
2022-01-06 10:38 ` Michael S. Tsirkin
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