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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	palmer@dabbelt.com, alistair23@gmail.com,
	Bin Meng <bin.meng@windriver.com>,
	bmeng.cn@gmail.com
Subject: [PATCH 1/2] target/riscv: Set the opcode in DisasContext
Date: Fri, 10 Dec 2021 16:26:37 +1000	[thread overview]
Message-ID: <20211210062638.824672-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211210062638.824672-1-alistair.francis@opensource.wdc.com>

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..24251bc8cc 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -586,6 +586,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         if (!has_ext(ctx, RVC)) {
             gen_exception_illegal(ctx);
         } else {
+            ctx->opcode = opcode;
             ctx->pc_succ_insn = ctx->base.pc_next + 2;
             if (!decode_insn16(ctx, opcode)) {
                 gen_exception_illegal(ctx);
@@ -596,6 +597,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         opcode32 = deposit32(opcode32, 16, 16,
                              translator_lduw(env, &ctx->base,
                                              ctx->base.pc_next + 2));
+        ctx->opcode = opcode32;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         if (!decode_insn32(ctx, opcode32)) {
             gen_exception_illegal(ctx);
-- 
2.31.1



  reply	other threads:[~2021-12-10  6:35 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-10  6:26 [PATCH 0/2] RISC-V: Populate mtval and stval Alistair Francis
2021-12-10  6:26 ` Alistair Francis [this message]
2021-12-10 15:28   ` [PATCH 1/2] target/riscv: Set the opcode in DisasContext Richard Henderson
2021-12-10  6:26 ` [PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2021-12-10 15:11   ` Richard Henderson

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