From: Nikita Shubin <nikita.shubin@maquefel.me>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-riscv@nongnu.org, Nikita Shubin <n.shubin@yadro.com>,
Bin Meng <bin.meng@windriver.com>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
atishp@atishpatra.org, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] target/riscv/pmp: fix no pmp illegal intrs
Date: Wed, 15 Dec 2021 10:57:59 +0300 [thread overview]
Message-ID: <20211215105759.011995e7@redslave.neermore.group> (raw)
In-Reply-To: <b165ef0f-3336-f4e5-61ee-b3d8cf9e02c0@linaro.org>
Hello Richard!
On Tue, 14 Dec 2021 13:13:57 -0800
Richard Henderson <richard.henderson@linaro.org> wrote:
> On 12/14/21 1:12 PM, Richard Henderson wrote:
> > On 12/14/21 1:26 AM, Nikita Shubin wrote:
> >> - if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
> >> + if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> >> + !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
> >
> > When would the number of rules become non-zero with PMP disabled?
> > When does this test make a difference?
>
> Oh, nevermind, I see what you mean.
>
Np, let me explain in details:
The ISA states:
> Platforms vary widely in demands for physical memory protection, and
> some platforms may provide other PMP structures in addition to or
> instead of the scheme described in this section.
So we might don't have PMP at all, but if we set
qdev_prop_set_bit(DEVICE(obj), "pmp", false);
for some CPU we still end up in illegal inst on mret, cause we get
pmp_get_num_rules(env) == 0, becouse we have no PMP which leads to zero
available rules.
>
> r~
>
next prev parent reply other threads:[~2021-12-15 8:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-14 9:26 [PATCH] target/riscv/pmp: fix no pmp illegal intrs Nikita Shubin
2021-12-14 21:12 ` Richard Henderson
2021-12-14 21:13 ` Richard Henderson
2021-12-15 7:57 ` Nikita Shubin [this message]
2021-12-21 6:34 ` Alistair Francis
2021-12-21 7:13 ` Nikita Shubin
2021-12-22 22:15 ` Alistair Francis
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