From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99678C433F5 for ; Wed, 15 Dec 2021 18:33:20 +0000 (UTC) Received: from localhost ([::1]:56118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mxZ5b-0007yi-Mm for qemu-devel@archiver.kernel.org; Wed, 15 Dec 2021 13:33:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mxXiZ-0005U3-09; Wed, 15 Dec 2021 12:05:27 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:5310) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mxXiW-0004pS-7T; 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Wed, 15 Dec 2021 17:04:56 +0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1BFGus7i45810106 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 15 Dec 2021 16:56:54 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 79A514204F; Wed, 15 Dec 2021 17:04:53 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 30C574204C; Wed, 15 Dec 2021 17:04:53 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with SMTP; Wed, 15 Dec 2021 17:04:53 +0000 (GMT) Received: from yukon.home (unknown [9.171.19.61]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 59706220295; Wed, 15 Dec 2021 18:04:52 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w Date: Wed, 15 Dec 2021 18:03:39 +0100 Message-Id: <20211215170357.321643-72-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211215170357.321643-1-clg@kaod.org> References: <20211215165847.321042-1-clg@kaod.org> <20211215170357.321643-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FHOCX4pSPwn73A9yYrnZOshrkRB662Jp X-Proofpoint-ORIG-GUID: MNp08btM9-d-S7AxNuKaqZ8GYWC10OYf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-15_10,2021-12-14_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1034 mlxlogscore=801 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112150098 Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Daniel Henrique Barboza , Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Daniel Henrique Barboza Calling pmu_update_cycles() on every PMC read/write operation ensures that the values being fetched are up to date with the current PMU state. In theory we can get away by just trapping PMCs reads, but we're going to trap PMC writes to deal with counter overflow logic later on. Let's put the required wiring for that and make our lives a bit easier in the next patches. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-4-danielhb413@gmail.com> Signed-off-by: C=C3=A9dric Le Goater --- target/ppc/helper.h | 2 ++ target/ppc/spr_tcg.h | 2 ++ target/ppc/cpu_init.c | 12 ++++++------ target/ppc/power8-pmu.c | 14 ++++++++++++++ target/ppc/power8-pmu-regs.c.inc | 29 +++++++++++++++++++++++++++-- 5 files changed, 51 insertions(+), 8 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 0e6cf2d09d4e..984d03181a52 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) +DEF_HELPER_2(read_pmc, tl, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index eb1d0c2bf0dc..1e79a0522aac 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn= ); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); @@ -35,6 +36,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gpr= n); void spr_read_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_tbl(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cfa605a76b84..ceb325b311fb 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6266,27 +6266,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCSt= ate *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 5e689144d712..7131f52ccc5d 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -133,6 +133,20 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulo= ng value) hreg_compute_hflags(env); } =20 +target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) +{ + pmu_update_cycles(env); + + return env->spr[sprn]; +} + +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[sprn] =3D value; +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-reg= s.c.inc index fbb89776414e..f0c9cc343b3d 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -181,13 +181,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sp= rn, int gprn) tcg_temp_free(masked_gprn); } =20 +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) +{ + TCGv_i32 t_sprn =3D tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); + + tcg_temp_free_i32(t_sprn); +} + void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) { if (!spr_groupA_read_allowed(ctx)) { return; } =20 - spr_read_ureg(ctx, gprn, sprn); + spr_read_PMC(ctx, gprn, sprn + 0x10); } =20 void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) @@ -206,13 +216,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gpr= n, int sprn) spr_read_PMC14_ureg(ctx, gprn, sprn); } =20 +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn =3D tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} + void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) { if (!spr_groupA_write_allowed(ctx)) { return; } =20 - spr_write_ureg(ctx, sprn, gprn); + spr_write_PMC(ctx, sprn + 0x10, gprn); } =20 void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) @@ -280,4 +300,9 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int= gprn) { spr_write_generic(ctx, sprn, gprn); } + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ --=20 2.31.1