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[83.50.185.174]) by smtp.gmail.com with ESMTPSA id u12sm2927470wrf.60.2021.12.15.12.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Dec 2021 12:57:05 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 0/3] hw/sd/sdhci: Fix DMA re-entrancy issue Date: Wed, 15 Dec 2021 21:56:53 +0100 Message-Id: <20211215205656.488940-1-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.129.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.719, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , qemu-block@nongnu.org, David Hildenbrand , Jason Wang , Bin Meng , Li Qiang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , Qiuhao Li , Darren Kenny , Bandan Das , Gerd Hoffmann , Stefan Hajnoczi , "Edgar E . Iglesias" , Alexander Bulekov , Paolo Bonzini , Mauro Matteo Cascella , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi,=0D =0D This series is an attempt to fix the DMA re-entrancy problem=0D on the SDHCI device. OSS-Fuzz found it and Alexander generated=0D a helpful reproducer.=0D =0D By setting the MemTxAttrs::memory bit before doing DMA transactions,=0D the flatview API will return MEMTX_BUS_ERROR if the transaction=0D targets a non-memory (a device), which is usually how DMA-reentrancy=0D bugs are exploited.=0D =0D On real hardware, the checks are on the interconnect bus, not in=0D the SDHCI block. However QEMU blocks aren't modelled that way.=0D Using the flatview API seems (to me) the simplest and closer=0D to hardware, it is a generic API and we can use it to trace=0D bus transactions on all blocks.=0D =0D Note this series is simply one example to fix the generic=0D issues. The important changes are in the previous series:=0D https://lore.kernel.org/qemu-devel/20211215182421.418374-1-philmd@redhat.co= m/=0D Based-on: <20211215182421.418374-1-philmd@redhat.com>=0D "physmem: Have flatview API check bus permission from MemTxAttrs"=0D =0D Cc: Mauro Matteo Cascella =0D Cc: Qiuhao Li =0D Cc: Peter Xu =0D Cc: Jason Wang =0D Cc: David Hildenbrand =0D Cc: Gerd Hoffmann =0D Cc: Peter Maydell =0D Cc: Li Qiang =0D Cc: Thomas Huth =0D Cc: Laurent Vivier =0D Cc: Bandan Das =0D Cc: Edgar E. Iglesias =0D Cc: Darren Kenny =0D Cc: Bin Meng =0D Cc: Paolo Bonzini =0D Cc: Alexander Bulekov =0D Cc: Stefan Hajnoczi =0D =0D Philippe Mathieu-Daud=C3=A9 (3):=0D hw/sd/sdhci: Honor failed DMA transactions=0D hw/sd/sdhci: Prohibit DMA accesses to devices=0D tests/qtest/fuzz-sdcard-test: Add reproducer for OSS-Fuzz (Issue=0D 29225)=0D =0D hw/sd/sdhci.c | 35 ++++++++++++----=0D tests/qtest/fuzz-sdcard-test.c | 76 ++++++++++++++++++++++++++++++++++=0D 2 files changed, 102 insertions(+), 9 deletions(-)=0D =0D --=20=0D 2.33.1=0D =0D