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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=977d27bfe=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis =0D This is a few patches to cleanup some RISC-V hardware and mark the=0D Hyperisor extension as non experimental.=0D =0D v2:=0D - Add some more fixes=0D - Address review comments=0D =0D Alistair Francis (9):=0D hw/intc: sifive_plic: Add a reset function=0D hw/intc: sifive_plic: Cleanup the write function=0D hw/intc: sifive_plic: Cleanup the read function=0D hw/intc: sifive_plic: Cleanup remaining functions=0D target/riscv: Mark the Hypervisor extension as non experimental=0D target/riscv: Enable the Hypervisor extension by default=0D hw/riscv: Use error_fatal for SoC realisation=0D hw/riscv: virt: Allow support for 32 cores=0D hw/riscv: virt: Set the clock-frequency=0D =0D include/hw/riscv/virt.h | 2 +-=0D hw/intc/sifive_plic.c | 254 +++++++++++--------------------------=0D hw/riscv/microchip_pfsoc.c | 2 +-=0D hw/riscv/opentitan.c | 2 +-=0D hw/riscv/sifive_e.c | 2 +-=0D hw/riscv/sifive_u.c | 2 +-=0D hw/riscv/virt.c | 1 +=0D target/riscv/cpu.c | 2 +-=0D 8 files changed, 83 insertions(+), 184 deletions(-)=0D =0D -- =0D 2.31.1=0D =0D