From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
alistair23@gmail.com, Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
bmeng.cn@gmail.com
Subject: [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function
Date: Thu, 16 Dec 2021 14:54:19 +1000 [thread overview]
Message-ID: <20211216045427.757779-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211216045427.757779-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..a9f7a1bfb0 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -355,6 +355,23 @@ static const MemoryRegionOps sifive_plic_ops = {
}
};
+static void sifive_plic_reset(DeviceState *dev)
+{
+ SiFivePLICState *s = SIFIVE_PLIC(dev);
+ int i;
+
+ memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
+ memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
+ memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
+ memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
+ memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
+
+ for (i = 0; i < s->num_harts; i++) {
+ qemu_set_irq(s->m_external_irqs[i], 0);
+ qemu_set_irq(s->s_external_irqs[i], 0);
+ }
+}
+
/*
* parse PLIC hart/mode address offset config
*
@@ -501,6 +518,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->reset = sifive_plic_reset;
device_class_set_props(dc, sifive_plic_properties);
dc->realize = sifive_plic_realize;
dc->vmsd = &vmstate_sifive_plic;
--
2.31.1
next prev parent reply other threads:[~2021-12-16 4:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 4:54 [PATCH v2 0/9] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-16 4:54 ` Alistair Francis [this message]
2021-12-16 8:16 ` [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function Philippe Mathieu-Daudé
2021-12-21 8:00 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-21 8:22 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-16 5:59 ` Anup Patel
2021-12-20 2:52 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 2:53 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-20 7:38 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2021-12-16 5:58 ` Anup Patel
2021-12-16 8:18 ` Philippe Mathieu-Daudé
2021-12-20 5:41 ` Alistair Francis
2021-12-20 7:39 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 7:51 ` Bin Meng
2021-12-21 6:32 ` Alistair Francis
2021-12-21 6:56 ` Bin Meng
2022-02-22 15:41 ` Peter Maydell
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