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envelope-from=prvs=977d27bfe=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/intc/sifive_plic.c | 76 +++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index a9f7a1bfb0..698492ce77 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -33,6 +33,11 @@ =20 #define RISCV_DEBUG_PLIC 0 =20 +static bool addr_between(uint32_t addr, uint32_t base, uint32_t num) +{ + return addr >=3D base && addr - base < num; +} + static PLICMode char_to_mode(char c) { switch (c) { @@ -269,80 +274,53 @@ static void sifive_plic_write(void *opaque, hwaddr = addr, uint64_t value, { SiFivePLICState *plic =3D opaque; =20 - /* writes must be 4 byte words */ - if ((addr & 0x3) !=3D 0) { - goto err; - } - - if (addr >=3D plic->priority_base && /* 4 bytes per source */ - addr < plic->priority_base + (plic->num_sources << 2)) - { + if (addr_between(addr, plic->priority_base, plic->num_sources << 2))= { uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; + plic->source_priority[irq] =3D value & 7; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: irq=3D%d priority=3D%d\n", - irq, plic->source_priority[irq]); - } sifive_plic_update(plic); - return; - } else if (addr >=3D plic->pending_base && /* 1 bit per source */ - addr < plic->pending_base + (plic->num_sources >> 3)) - { + } else if (addr_between(addr, plic->pending_base, + plic->num_sources >> 3)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pending write: 0x%" HWADDR_PRIx "", __func__, addr); - return; - } else if (addr >=3D plic->enable_base && /* 1 bit per source */ - addr < plic->enable_base + plic->num_addrs * plic->enable_stride= ) - { + } else if (addr_between(addr, plic->enable_base, + plic->num_addrs * plic->enable_stride)) { uint32_t addrid =3D (addr - plic->enable_base) / plic->enable_st= ride; uint32_t wordid =3D (addr & (plic->enable_stride - 1)) >> 2; + if (wordid < plic->bitfield_words) { plic->enable[addrid * plic->bitfield_words + wordid] =3D val= ue; - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write enable: hart%d-%c word=3D%d value=3D= %x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), wordid= , - plic->enable[addrid * plic->bitfield_words + wordid]= ); - } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid enable write 0x%" HWADDR_PRIx "\n= ", + __func__, addr); } - } else if (addr >=3D plic->context_base && /* 4 bytes per reg */ - addr < plic->context_base + plic->num_addrs * plic->context_stri= de) - { + } else if (addr_between(addr, plic->context_base, + plic->num_addrs * plic->context_stride)) { uint32_t addrid =3D (addr - plic->context_base) / plic->context_= stride; uint32_t contextid =3D (addr & (plic->context_stride - 1)); + if (contextid =3D=3D 0) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write priority: hart%d-%c priority=3D%x\= n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - plic->target_priority[addrid]); - } if (value <=3D plic->num_priorities) { plic->target_priority[addrid] =3D value; sifive_plic_update(plic); } - return; } else if (contextid =3D=3D 4) { - if (RISCV_DEBUG_PLIC) { - qemu_log("plic: write claim: hart%d-%c irq=3D%x\n", - plic->addr_config[addrid].hartid, - mode_to_char(plic->addr_config[addrid].mode), - (uint32_t)value); - } if (value < plic->num_sources) { sifive_plic_set_claimed(plic, value, false); sifive_plic_update(plic); } - return; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid context write 0x%" HWADDR_PRIx "\= n", + __func__, addr); } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); } - -err: - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Invalid register write 0x%" HWADDR_PRIx "\n", - __func__, addr); } =20 static const MemoryRegionOps sifive_plic_ops =3D { --=20 2.31.1