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Fri, 17 Dec 2021 19:28:31 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7E53A4040; Fri, 17 Dec 2021 19:28:30 +0000 (GMT) Received: from li-e979b1cc-23ba-11b2-a85c-dfd230f6cf82 (unknown [9.171.63.32]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Fri, 17 Dec 2021 19:28:30 +0000 (GMT) Date: Fri, 17 Dec 2021 20:28:18 +0100 From: Halil Pasic To: Pierre Morel Subject: Re: [PATCH qemu] s390x/css: fix PMCW invalid mask Message-ID: <20211217202818.7e843a1d.pasic@linux.ibm.com> In-Reply-To: <7143886b-ffa2-e5f7-e7fe-b06212522824@linux.ibm.com> References: <20211216131657.1057978-1-nrb@linux.ibm.com> <20211217145811.71dd0a70.pasic@linux.ibm.com> <7143886b-ffa2-e5f7-e7fe-b06212522824@linux.ibm.com> Organization: IBM X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 57-yYX5lieEz6gyiUR561kDSuyuOru1Y X-Proofpoint-ORIG-GUID: w2yeHFRp5qKmOqxmSZPVctE3u0Afh6Iv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-17_07,2021-12-16_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112170104 Received-SPF: pass client-ip=148.163.156.1; envelope-from=pasic@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Nico Boehr , frankja@linux.ibm.com, cohuck@redhat.com, qemu-devel@nongnu.org, Halil Pasic , borntraeger@de.ibm.com, qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 17 Dec 2021 18:13:47 +0100 Pierre Morel wrote: > >> Previously, we required bits 5, 6 and 7 to be zero (0x07 == 0b111). But, > >> as per the principles of operation, bit 5 is ignored in MSCH and bits 0, > >> 1, 6 and 7 need to be zero. > > > > On a second thought, don't we have to make sure then that bit 5 is > > ignored? > > > > static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) > > { > > int i; > > > > dest->intparm = be32_to_cpu(src->intparm); > > dest->flags = be16_to_cpu(src->flags); > > dest->devno = be16_to_cpu(src->devno); > > > > Here we seem to grab flags as a whole, but actually we would have to > > mask of bit 5. > > Why? > If this bit is ignored by the machine shouldn't we just ignore it? > Forcing it to 0 or to 1 is purely arbitrary no? We do the masking later on: IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) { [..] /* Only update the program-modifiable fields. */ schib->pmcw.intparm = schib_copy.pmcw.intparm; oldflags = schib->pmcw.flags; schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | PMCW_FLAGS_MASK_MP); schib->pmcw.flags |= schib_copy.pmcw.flags & (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | PMCW_FLAGS_MASK_MP); [..] I just didn't read far enough. We do that for a while now. The PoP says that the machine shall ignore other fields of the PMCW when an MSCH is performed. I.e. we should not update "our" pmcw.flags bit 5 from 0 to 1 even if 1 was supplied, and thus STSCH should keep storing the bit 5 as 0 even if there was a MSCH with bit 5 set. Regards, Halil