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([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 9JqvrWKUhZJU for ; Sun, 19 Dec 2021 20:57:15 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.165.68]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4JHS4S5kpkz1RtVG; Sun, 19 Dec 2021 20:57:12 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis Subject: [PULL 00/88] riscv-to-apply queue Date: Mon, 20 Dec 2021 14:55:37 +1000 Message-Id: <20211220045705.62174-1-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The following changes since commit 212a33d3b0c65ae2583bb1d06cb140cd089089= 4c: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagin= g (2021-12-19 16:36:10 -0800) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211220-1 for you to fetch changes up to 7e322a7f23a60b0e181b55ef722fdf390ec4e463: hw/riscv: Use load address rather than entry point for fw_dynamic next_= addr (2021-12-20 14:53:31 +1000) ---------------------------------------------------------------- First RISC-V PR for QEMU 7.0 - Add support for ratified 1.0 Vector extension - Drop support for draft 0.7.1 Vector extension - Support Zfhmin and Zfh extensions - Improve kernel loading for non-Linux platforms ---------------------------------------------------------------- Frank Chang (75): target/riscv: zfh: add Zfh cpu property target/riscv: zfh: implement zfhmin extension target/riscv: zfh: add Zfhmin cpu property target/riscv: drop vector 0.7.1 and add 1.0 support target/riscv: Use FIELD_EX32() to extract wd field target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty target/riscv: rvv-1.0: introduce writable misa.v field target/riscv: rvv-1.0: add translation-time vector context status target/riscv: rvv-1.0: remove rvv related codes from fcsr registers target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr r= egisters target/riscv: rvv-1.0: remove MLEN calculations target/riscv: rvv-1.0: add fractional LMUL target/riscv: rvv-1.0: add VMA and VTA target/riscv: rvv-1.0: update check functions target/riscv: introduce more imm value modes in translator function= s target/riscv: rvv:1.0: add translation-time nan-box helper function target/riscv: rvv-1.0: remove amo operations instructions target/riscv: rvv-1.0: configure instructions target/riscv: rvv-1.0: stride load and store instructions target/riscv: rvv-1.0: index load and store instructions target/riscv: rvv-1.0: fix address index overflow bug of indexed lo= ad/store insns target/riscv: rvv-1.0: fault-only-first unit stride load target/riscv: rvv-1.0: load/store whole register instructions target/riscv: rvv-1.0: update vext_max_elems() for load/store insns target/riscv: rvv-1.0: take fractional LMUL into vector max element= s calculation target/riscv: rvv-1.0: floating-point square-root instruction target/riscv: rvv-1.0: floating-point classify instructions target/riscv: rvv-1.0: count population in mask instruction target/riscv: rvv-1.0: find-first-set mask bit instruction target/riscv: rvv-1.0: set-X-first mask bit instructions target/riscv: rvv-1.0: iota instruction target/riscv: rvv-1.0: element index instruction target/riscv: rvv-1.0: allow load element with sign-extended target/riscv: rvv-1.0: register gather instructions target/riscv: rvv-1.0: integer scalar move instructions target/riscv: rvv-1.0: floating-point move instruction target/riscv: rvv-1.0: floating-point scalar move instructions target/riscv: rvv-1.0: whole register move instructions target/riscv: rvv-1.0: integer extension instructions target/riscv: rvv-1.0: single-width averaging add and subtract inst= ructions target/riscv: rvv-1.0: single-width bit shift instructions target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow target/riscv: rvv-1.0: narrowing integer right shift instructions target/riscv: rvv-1.0: widening integer multiply-add instructions target/riscv: rvv-1.0: single-width saturating add and subtract ins= tructions target/riscv: rvv-1.0: integer comparison instructions target/riscv: rvv-1.0: floating-point compare instructions target/riscv: rvv-1.0: mask-register logical instructions target/riscv: rvv-1.0: slide instructions target/riscv: rvv-1.0: floating-point slide instructions target/riscv: rvv-1.0: narrowing fixed-point clip instructions target/riscv: rvv-1.0: single-width floating-point reduction target/riscv: rvv-1.0: widening floating-point reduction instructio= ns target/riscv: rvv-1.0: single-width scaling shift instructions target/riscv: rvv-1.0: remove widening saturating scaled multiply-a= dd target/riscv: rvv-1.0: remove vmford.vv and vmford.vf target/riscv: rvv-1.0: remove integer extract instruction target/riscv: rvv-1.0: floating-point min/max instructions target/riscv: introduce floating-point rounding mode enum target/riscv: rvv-1.0: floating-point/integer type-convert instruct= ions target/riscv: rvv-1.0: widening floating-point/integer type-convert target/riscv: add "set round to odd" rounding mode helper function target/riscv: rvv-1.0: narrowing floating-point/integer type-conver= t target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits target/riscv: rvv-1.0: implement vstart CSR target/riscv: rvv-1.0: trigger illegal instruction exception if frm= is not valid target/riscv: rvv-1.0: floating-point reciprocal square-root estima= te instruction target/riscv: rvv-1.0: floating-point reciprocal estimate instructi= on target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 target/riscv: rvv-1.0: add vsetivli instruction target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() target/riscv: rvv-1.0: add vector unit-stride mask load/store insns target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.= mm and vmorn.mm target/riscv: rvv-1.0: update opivv_vadc_check() comment target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing i= nstructions Greentime Hu (1): target/riscv: rvv-1.0: add vlenb register Hsiangkai Wang (1): target/riscv: gdb: support vector registers for rv64 & rv32 Jessica Clarke (1): hw/riscv: Use load address rather than entry point for fw_dynamic n= ext_addr Khem Raj (1): riscv: Set 5.4 as minimum kernel version for riscv32 Kito Cheng (5): target/riscv: zfh: half-precision load and store target/riscv: zfh: half-precision computational target/riscv: zfh: half-precision convert and move target/riscv: zfh: half-precision floating-point compare target/riscv: zfh: half-precision floating-point classify LIU Zhiwei (3): target/riscv: rvv-1.0: add mstatus VS field target/riscv: rvv-1.0: add sstatus VS field target/riscv: rvv-1.0: add vcsr register Vineet Gupta (1): target/riscv: Enable bitmanip Zb[abcs] instructions linux-user/riscv/target_syscall.h | 3 +- target/riscv/cpu.h | 63 +- target/riscv/cpu_bits.h | 10 + target/riscv/helper.h | 464 ++-- target/riscv/internals.h | 40 +- target/riscv/insn32.decode | 332 +-- hw/riscv/boot.c | 13 +- target/riscv/cpu.c | 28 +- target/riscv/cpu_helper.c | 39 +- target/riscv/csr.c | 63 +- target/riscv/fpu_helper.c | 197 +- target/riscv/gdbstub.c | 184 ++ target/riscv/translate.c | 93 +- target/riscv/vector_helper.c | 3601 +++++++++++++++--------= ------ target/riscv/insn_trans/trans_rvv.c.inc | 2429 ++++++++++++------- target/riscv/insn_trans/trans_rvzfh.c.inc | 537 +++++ 16 files changed, 4997 insertions(+), 3099 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc