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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-10-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++++++ target/riscv/csr.c | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bb62da7549..8dc6aa62c6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -60,9 +60,16 @@ #define CSR_VSTART 0x008 #define CSR_VXSAT 0x009 #define CSR_VXRM 0x00a +#define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 =20 +/* VCSR fields */ +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c522260986..832ccdcf33 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -336,6 +336,22 @@ static RISCVException write_vstart(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_= SHIFT); + return RISCV_EXCP_NONE; +} + +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxrm =3D (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; + env->vxsat =3D (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; + return RISCV_EXCP_NONE; +} + /* User Timers and Counters */ static RISCVException read_instret(CPURISCVState *env, int csrno, target_ulong *val) @@ -1816,6 +1832,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart = }, [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat = }, [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm = }, + [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr = }, [CSR_VL] =3D { "vl", vs, read_vl = }, [CSR_VTYPE] =3D { "vtype", vs, read_vtype = }, /* User Timers and Counters */ --=20 2.31.1