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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-14-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 26 ++++++++++++++------------ target/riscv/translate.c | 16 ++++++++++++++-- target/riscv/vector_helper.c | 16 ++++++++++++++-- 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eee2a2b19e..17414bfff7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -102,10 +102,10 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 -FIELD(VTYPE, VLMUL, 0, 2) -FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VLMUL, 0, 3) +FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VEDIV, 8, 2) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { @@ -403,18 +403,20 @@ typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) -FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, LMUL, 3, 3) FIELD(TB_FLAGS, SEW, 6, 3) -FIELD(TB_FLAGS, VILL, 9, 1) +/* Skip MSTATUS_VS (0x600) bits */ +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) +FIELD(TB_FLAGS, VILL, 12, 1) +/* Skip MSTATUS_FS (0x6000) bits */ /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 10, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2) +FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) +FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. = */ -FIELD(TB_FLAGS, XL, 15, 2) +FIELD(TB_FLAGS, XL, 20, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 17, 1) +FIELD(TB_FLAGS, PM_ENABLED, 22, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 17101d854b..3688e80d03 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,19 @@ typedef struct DisasContext { bool hlsx; /* vector extension */ bool vill; - uint8_t lmul; + /* + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ + int8_t lmul; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -690,7 +702,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); - ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3)= ; ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs =3D cs; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ac6c7298bc..866bfb3571 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VM); } =20 -static inline uint32_t vext_lmul(uint32_t desc) +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } =20 static uint32_t vext_wd(uint32_t desc) --=20 2.31.1