From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 27/88] target/riscv: rvv-1.0: configure instructions
Date: Mon, 20 Dec 2021 14:56:04 +1000 [thread overview]
Message-ID: <20211220045705.62174-28-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-20-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 14 +++++-
target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++--------------
2 files changed, 40 insertions(+), 36 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bf976d364f..78fae78284 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
+ uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
bool vill = FIELD_EX64(s2, VTYPE, VILL);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ if (lmul & 4) {
+ /* Fractional LMUL. */
+ if (lmul == 4 ||
+ cpu->cfg.elen >> (8 - lmul) < sew) {
+ vill = true;
+ }
+ }
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
env->vl = 0;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index afec187333..049688d83a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -120,59 +120,51 @@ static bool require_noover(const int8_t dst, const int8_t dst_lmul,
return !is_overlapped(dst, dst_size, src, src_size);
}
-static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
{
- TCGv s1, s2, dst;
+ TCGv s1, dst;
- if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
+ if (!require_rvv(s) || !has_ext(s, RVV)) {
return false;
}
- s2 = get_gpr(ctx, a->rs2, EXT_ZERO);
- dst = dest_gpr(ctx, a->rd);
+ dst = dest_gpr(s, rd);
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (rd == 0 && rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_constant_tl(RV_VLEN_MAX);
} else {
- s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ s1 = get_gpr(s, rs1, EXT_ZERO);
}
+
gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(ctx, a->rd, dst);
- mark_vs_dirty(ctx);
+ gen_set_gpr(s, rd, dst);
+ mark_vs_dirty(s);
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
-}
+ s->base.is_jmp = DISAS_NORETURN;
-static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
-{
- TCGv s1, s2, dst;
-
- if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
- return false;
+ if (rd == 0 && rs1 == 0) {
+ tcg_temp_free(s1);
}
- s2 = tcg_constant_tl(a->zimm);
- dst = dest_gpr(ctx, a->rd);
+ return true;
+}
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_constant_tl(RV_VLEN_MAX);
- } else {
- s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
- }
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(ctx, a->rd, dst);
- mark_vs_dirty(ctx);
+static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a)
+{
+ TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO);
+ return do_vsetvl(s, a->rd, a->rs1, s2);
+}
- gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
+static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
+{
+ TCGv s2 = tcg_constant_tl(a->zimm);
+ return do_vsetvl(s, a->rd, a->rs1, s2);
}
/* vector register offset from env */
--
2.31.1
next prev parent reply other threads:[~2021-12-20 5:23 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 4:55 [PULL 00/88] riscv-to-apply queue Alistair Francis
2021-12-20 4:55 ` [PULL 01/88] target/riscv: zfh: half-precision load and store Alistair Francis
2021-12-20 4:55 ` [PULL 02/88] target/riscv: zfh: half-precision computational Alistair Francis
2021-12-20 4:55 ` [PULL 03/88] target/riscv: zfh: half-precision convert and move Alistair Francis
2021-12-20 4:55 ` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare Alistair Francis
2021-12-20 4:55 ` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify Alistair Francis
2021-12-20 4:55 ` [PULL 06/88] target/riscv: zfh: add Zfh cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 07/88] target/riscv: zfh: implement zfhmin extension Alistair Francis
2021-12-20 4:55 ` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support Alistair Francis
2021-12-20 4:55 ` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field Alistair Francis
2021-12-20 4:55 ` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Alistair Francis
2021-12-20 4:55 ` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field Alistair Francis
2021-12-20 4:55 ` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status Alistair Francis
2021-12-20 4:55 ` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers Alistair Francis
2021-12-20 4:55 ` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register Alistair Francis
2021-12-20 4:55 ` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register Alistair Francis
2021-12-20 4:55 ` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers Alistair Francis
2021-12-20 4:55 ` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations Alistair Francis
2021-12-20 4:55 ` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL Alistair Francis
2021-12-20 4:55 ` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA Alistair Francis
2021-12-20 4:56 ` [PULL 23/88] target/riscv: rvv-1.0: update check functions Alistair Francis
2021-12-20 4:56 ` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions Alistair Francis
2021-12-20 4:56 ` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function Alistair Francis
2021-12-20 4:56 ` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions Alistair Francis
2021-12-20 4:56 ` Alistair Francis [this message]
2021-12-20 4:56 ` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions Alistair Francis
2021-12-20 4:56 ` [PULL 29/88] target/riscv: rvv-1.0: index " Alistair Francis
2021-12-20 4:56 ` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load Alistair Francis
2021-12-20 4:56 ` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions Alistair Francis
2021-12-20 4:56 ` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Alistair Francis
2021-12-20 4:56 ` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction Alistair Francis
2021-12-20 4:56 ` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions Alistair Francis
2021-12-20 4:56 ` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction Alistair Francis
2021-12-20 4:56 ` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction Alistair Francis
2021-12-20 4:56 ` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions Alistair Francis
2021-12-20 4:56 ` [PULL 40/88] target/riscv: rvv-1.0: iota instruction Alistair Francis
2021-12-20 4:56 ` [PULL 41/88] target/riscv: rvv-1.0: element index instruction Alistair Francis
2021-12-20 4:56 ` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended Alistair Francis
2021-12-20 4:56 ` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions Alistair Francis
2021-12-20 4:56 ` [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction Alistair Francis
2021-12-20 4:56 ` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 47/88] target/riscv: rvv-1.0: whole register " Alistair Francis
2021-12-20 4:56 ` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions Alistair Francis
2021-12-20 4:56 ` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow Alistair Francis
2021-12-20 4:56 ` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions Alistair Francis
2021-12-20 4:56 ` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions Alistair Francis
2021-12-20 4:56 ` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions Alistair Francis
2021-12-20 4:56 ` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions Alistair Francis
2021-12-20 4:56 ` [PULL 58/88] target/riscv: rvv-1.0: slide instructions Alistair Francis
2021-12-20 4:56 ` [PULL 59/88] target/riscv: rvv-1.0: floating-point " Alistair Francis
2021-12-20 4:56 ` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Alistair Francis
2021-12-20 4:56 ` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction Alistair Francis
2021-12-20 4:56 ` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions Alistair Francis
2021-12-20 4:56 ` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Alistair Francis
2021-12-20 4:56 ` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Alistair Francis
2021-12-20 4:56 ` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction Alistair Francis
2021-12-20 4:56 ` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions Alistair Francis
2021-12-20 4:56 ` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum Alistair Francis
2021-12-20 4:56 ` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Alistair Francis
2021-12-20 4:56 ` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function Alistair Francis
2021-12-20 4:56 ` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Alistair Francis
2021-12-20 4:56 ` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR Alistair Francis
2021-12-20 4:56 ` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Alistair Francis
2021-12-20 4:56 ` [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32 Alistair Francis
2021-12-20 4:56 ` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Alistair Francis
2021-12-20 4:56 ` [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal " Alistair Francis
2021-12-20 4:56 ` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Alistair Francis
2021-12-20 4:56 ` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction Alistair Francis
2021-12-20 4:56 ` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Alistair Francis
2021-12-20 4:56 ` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Alistair Francis
2021-12-20 4:57 ` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Alistair Francis
2021-12-20 4:57 ` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment Alistair Francis
2021-12-20 4:57 ` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions Alistair Francis
2021-12-20 4:57 ` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32 Alistair Francis via
2021-12-20 4:57 ` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions Alistair Francis
2021-12-20 4:57 ` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr Alistair Francis
2021-12-20 21:19 ` [PULL 00/88] riscv-to-apply queue Richard Henderson
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