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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-20-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 14 +++++- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++-------------- 2 files changed, 40 insertions(+), 36 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bf976d364f..78fae78284 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, targe= t_ulong s1, { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); + uint64_t lmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); bool vill =3D FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D= 0)) { + if (lmul & 4) { + /* Fractional LMUL. */ + if (lmul =3D=3D 4 || + cpu->cfg.elen >> (8 - lmul) < sew) { + vill =3D true; + } + } + + if ((sew > cpu->cfg.elen) + || vill + || (ediv !=3D 0) + || (reserved !=3D 0)) { /* only set vill bit. */ env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); env->vl =3D 0; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_= trans/trans_rvv.c.inc index afec187333..049688d83a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -120,59 +120,51 @@ static bool require_noover(const int8_t dst, const = int8_t dst_lmul, return !is_overlapped(dst, dst_size, src, src_size); } =20 -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { - TCGv s1, s2, dst; + TCGv s1, dst; =20 - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { + if (!require_rvv(s) || !has_ext(s, RVV)) { return false; } =20 - s2 =3D get_gpr(ctx, a->rs2, EXT_ZERO); - dst =3D dest_gpr(ctx, a->rd); + dst =3D dest_gpr(s, rd); =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL *= / - if (a->rs1 =3D=3D 0) { + if (rd =3D=3D 0 && rs1 =3D=3D 0) { + s1 =3D tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_constant_tl(RV_VLEN_MAX); } else { - s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); + s1 =3D get_gpr(s, rs1, EXT_ZERO); } + gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); =20 - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp =3D DISAS_NORETURN; - return true; -} + s->base.is_jmp =3D DISAS_NORETURN; =20 -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) -{ - TCGv s1, s2, dst; - - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { - return false; + if (rd =3D=3D 0 && rs1 =3D=3D 0) { + tcg_temp_free(s1); } =20 - s2 =3D tcg_constant_tl(a->zimm); - dst =3D dest_gpr(ctx, a->rd); + return true; +} =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL *= / - if (a->rs1 =3D=3D 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ - s1 =3D tcg_constant_tl(RV_VLEN_MAX); - } else { - s1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); - } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) +{ + TCGv s2 =3D get_gpr(s, a->rs2, EXT_ZERO); + return do_vsetvl(s, a->rd, a->rs1, s2); +} =20 - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp =3D DISAS_NORETURN; - return true; +static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a) +{ + TCGv s2 =3D tcg_constant_tl(a->zimm); + return do_vsetvl(s, a->rd, a->rs1, s2); } =20 /* vector register offset from env */ --=20 2.31.1