From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 29/88] target/riscv: rvv-1.0: index load and store instructions
Date: Mon, 20 Dec 2021 14:56:06 +1000 [thread overview]
Message-ID: <20211220045705.62174-30-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-22-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 67 +++++++--------
target/riscv/insn32.decode | 21 +++--
target/riscv/vector_helper.c | 98 +++++++++------------
target/riscv/insn_trans/trans_rvv.c.inc | 110 +++++++++++++-----------
4 files changed, 145 insertions(+), 151 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5a760fa4a3..1beca6dc0d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -136,41 +136,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2d8f0cbe7c..f34194d31c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -322,18 +322,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+# Vector ordered-indexed and unordered-indexed load insns.
+vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
+
# Vector ordered-indexed and unordered-indexed store insns.
-vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
-vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
-vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
+vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
# *** new major opcode OP-V ***
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9141292994..df45c1620c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -217,15 +217,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
}
-GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
-GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
-GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
-GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
-GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
-GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
-GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
-GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
-GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
@@ -393,8 +384,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -406,7 +396,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
+ probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
access_type);
}
/* load bytes from guest memory */
@@ -416,67 +406,63 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
+ abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
}
}
-#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \
+#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b)
-GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h)
-GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w)
-GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d)
-GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h)
-GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w)
-GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d)
-GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w)
-GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d)
-GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b)
-GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h)
-GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w)
-GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d)
-GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b)
-GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h)
-GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w)
-GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d)
-GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h)
-GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w)
-GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d)
-GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w)
-GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d)
-
-#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
+ LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
+GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h)
+GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w)
+GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d)
+GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b)
+GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h)
+GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w)
+GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d)
+GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b)
+GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h)
+GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w)
+GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d)
+GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b)
+GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h)
+GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w)
+GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d)
+
+#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ STORE_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
-GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
-GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
-GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
-GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
-GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
-GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
-GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
-GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
-GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
-GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
-GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
-GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
+GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
+GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
+GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
+GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
+GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
+GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
+GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
+GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
+GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
+GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
+GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
+GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
+GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
+GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
+GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
+GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
*** unit-stride fault-only-fisrt load instructions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8a4f75f724..6946d03340 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -803,31 +803,38 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[7][4] = {
- { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
- gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
- { NULL, gen_helper_vlxh_v_h,
- gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
- { NULL, NULL,
- gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
- { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
- gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
- { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
- gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
- { NULL, gen_helper_vlxhu_v_h,
- gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
- { NULL, NULL,
- gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
+ static gen_helper_ldst_index * const fns[4][4] = {
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v,
+ gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
+ gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
+ gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
+ gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[eew][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -835,11 +842,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
-/*
- * For vector indexed segment loads, the destination vector register
- * groups cannot overlap the source vector register group (specified by
- * `vs2`), else an illegal instruction exception is raised.
- */
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
{
return require_rvv(s) &&
@@ -847,33 +849,43 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
}
-GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei8_v, MO_8, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check)
-static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[4][4] = {
- { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
- gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
- { NULL, gen_helper_vsxh_v_h,
- gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
- { NULL, NULL,
- gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
- { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
- gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v,
+ gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
+ gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
+ gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
+ gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[eew][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -888,10 +900,10 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
}
-GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei8_v, MO_8, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check)
/*
*** unit stride fault-only-first load
--
2.31.1
next prev parent reply other threads:[~2021-12-20 5:45 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 4:55 [PULL 00/88] riscv-to-apply queue Alistair Francis
2021-12-20 4:55 ` [PULL 01/88] target/riscv: zfh: half-precision load and store Alistair Francis
2021-12-20 4:55 ` [PULL 02/88] target/riscv: zfh: half-precision computational Alistair Francis
2021-12-20 4:55 ` [PULL 03/88] target/riscv: zfh: half-precision convert and move Alistair Francis
2021-12-20 4:55 ` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare Alistair Francis
2021-12-20 4:55 ` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify Alistair Francis
2021-12-20 4:55 ` [PULL 06/88] target/riscv: zfh: add Zfh cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 07/88] target/riscv: zfh: implement zfhmin extension Alistair Francis
2021-12-20 4:55 ` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support Alistair Francis
2021-12-20 4:55 ` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field Alistair Francis
2021-12-20 4:55 ` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Alistair Francis
2021-12-20 4:55 ` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field Alistair Francis
2021-12-20 4:55 ` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status Alistair Francis
2021-12-20 4:55 ` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers Alistair Francis
2021-12-20 4:55 ` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register Alistair Francis
2021-12-20 4:55 ` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register Alistair Francis
2021-12-20 4:55 ` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers Alistair Francis
2021-12-20 4:55 ` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations Alistair Francis
2021-12-20 4:55 ` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL Alistair Francis
2021-12-20 4:55 ` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA Alistair Francis
2021-12-20 4:56 ` [PULL 23/88] target/riscv: rvv-1.0: update check functions Alistair Francis
2021-12-20 4:56 ` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions Alistair Francis
2021-12-20 4:56 ` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function Alistair Francis
2021-12-20 4:56 ` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions Alistair Francis
2021-12-20 4:56 ` [PULL 27/88] target/riscv: rvv-1.0: configure instructions Alistair Francis
2021-12-20 4:56 ` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions Alistair Francis
2021-12-20 4:56 ` Alistair Francis [this message]
2021-12-20 4:56 ` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load Alistair Francis
2021-12-20 4:56 ` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions Alistair Francis
2021-12-20 4:56 ` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Alistair Francis
2021-12-20 4:56 ` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction Alistair Francis
2021-12-20 4:56 ` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions Alistair Francis
2021-12-20 4:56 ` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction Alistair Francis
2021-12-20 4:56 ` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction Alistair Francis
2021-12-20 4:56 ` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions Alistair Francis
2021-12-20 4:56 ` [PULL 40/88] target/riscv: rvv-1.0: iota instruction Alistair Francis
2021-12-20 4:56 ` [PULL 41/88] target/riscv: rvv-1.0: element index instruction Alistair Francis
2021-12-20 4:56 ` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended Alistair Francis
2021-12-20 4:56 ` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions Alistair Francis
2021-12-20 4:56 ` [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction Alistair Francis
2021-12-20 4:56 ` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 47/88] target/riscv: rvv-1.0: whole register " Alistair Francis
2021-12-20 4:56 ` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions Alistair Francis
2021-12-20 4:56 ` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow Alistair Francis
2021-12-20 4:56 ` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions Alistair Francis
2021-12-20 4:56 ` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions Alistair Francis
2021-12-20 4:56 ` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions Alistair Francis
2021-12-20 4:56 ` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions Alistair Francis
2021-12-20 4:56 ` [PULL 58/88] target/riscv: rvv-1.0: slide instructions Alistair Francis
2021-12-20 4:56 ` [PULL 59/88] target/riscv: rvv-1.0: floating-point " Alistair Francis
2021-12-20 4:56 ` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Alistair Francis
2021-12-20 4:56 ` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction Alistair Francis
2021-12-20 4:56 ` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions Alistair Francis
2021-12-20 4:56 ` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Alistair Francis
2021-12-20 4:56 ` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Alistair Francis
2021-12-20 4:56 ` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction Alistair Francis
2021-12-20 4:56 ` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions Alistair Francis
2021-12-20 4:56 ` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum Alistair Francis
2021-12-20 4:56 ` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Alistair Francis
2021-12-20 4:56 ` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function Alistair Francis
2021-12-20 4:56 ` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Alistair Francis
2021-12-20 4:56 ` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR Alistair Francis
2021-12-20 4:56 ` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Alistair Francis
2021-12-20 4:56 ` [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32 Alistair Francis
2021-12-20 4:56 ` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Alistair Francis
2021-12-20 4:56 ` [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal " Alistair Francis
2021-12-20 4:56 ` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Alistair Francis
2021-12-20 4:56 ` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction Alistair Francis
2021-12-20 4:56 ` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Alistair Francis
2021-12-20 4:56 ` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Alistair Francis
2021-12-20 4:57 ` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Alistair Francis
2021-12-20 4:57 ` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment Alistair Francis
2021-12-20 4:57 ` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions Alistair Francis
2021-12-20 4:57 ` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32 Alistair Francis via
2021-12-20 4:57 ` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions Alistair Francis
2021-12-20 4:57 ` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr Alistair Francis
2021-12-20 21:19 ` [PULL 00/88] riscv-to-apply queue Richard Henderson
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