From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions
Date: Mon, 20 Dec 2021 14:56:21 +1000 [thread overview]
Message-ID: <20211220045705.62174-45-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-37-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.c.inc | 43 ++++++++++++++++++++-----
2 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4653a9679e..e33ec82fdf 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -634,8 +634,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
+vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
+vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 322fc5c4aa..c250943dde 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2978,27 +2978,54 @@ static void vec_element_storei(DisasContext *s, int vreg,
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
}
+/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
+static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
+{
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
+ TCGv_i64 t1;
+ TCGv dest;
+
+ t1 = tcg_temp_new_i64();
+ dest = tcg_temp_new();
+ /*
+ * load vreg and sign-extend to 64 bits,
+ * then truncate to XLEN bits before storing to gpr.
+ */
+ vec_element_loadi(s, t1, a->rs2, 0, true);
+ tcg_gen_trunc_i64_tl(dest, t1);
+ gen_set_gpr(s, a->rd, dest);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free(dest);
+
+ return true;
+ }
+ return false;
+}
+
/* vmv.s.x vd, rs1 # vd[0] = rs1 */
static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
{
- if (vext_check_isa_ill(s)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
/* This instruction ignores LMUL and vector register groups */
- int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+ TCGv s1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
- if (a->rs1 == 0) {
- goto done;
- }
t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+
+ /*
+ * load gpr and sign-extend to 64 bits,
+ * then truncate to SEW bits when storing to vreg.
+ */
+ s1 = get_gpr(s, a->rs1, EXT_NONE);
+ tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);
- done:
gen_set_label(over);
return true;
}
--
2.31.1
next prev parent reply other threads:[~2021-12-20 5:54 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 4:55 [PULL 00/88] riscv-to-apply queue Alistair Francis
2021-12-20 4:55 ` [PULL 01/88] target/riscv: zfh: half-precision load and store Alistair Francis
2021-12-20 4:55 ` [PULL 02/88] target/riscv: zfh: half-precision computational Alistair Francis
2021-12-20 4:55 ` [PULL 03/88] target/riscv: zfh: half-precision convert and move Alistair Francis
2021-12-20 4:55 ` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare Alistair Francis
2021-12-20 4:55 ` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify Alistair Francis
2021-12-20 4:55 ` [PULL 06/88] target/riscv: zfh: add Zfh cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 07/88] target/riscv: zfh: implement zfhmin extension Alistair Francis
2021-12-20 4:55 ` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support Alistair Francis
2021-12-20 4:55 ` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field Alistair Francis
2021-12-20 4:55 ` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Alistair Francis
2021-12-20 4:55 ` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field Alistair Francis
2021-12-20 4:55 ` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status Alistair Francis
2021-12-20 4:55 ` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers Alistair Francis
2021-12-20 4:55 ` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register Alistair Francis
2021-12-20 4:55 ` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register Alistair Francis
2021-12-20 4:55 ` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers Alistair Francis
2021-12-20 4:55 ` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations Alistair Francis
2021-12-20 4:55 ` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL Alistair Francis
2021-12-20 4:55 ` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA Alistair Francis
2021-12-20 4:56 ` [PULL 23/88] target/riscv: rvv-1.0: update check functions Alistair Francis
2021-12-20 4:56 ` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions Alistair Francis
2021-12-20 4:56 ` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function Alistair Francis
2021-12-20 4:56 ` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions Alistair Francis
2021-12-20 4:56 ` [PULL 27/88] target/riscv: rvv-1.0: configure instructions Alistair Francis
2021-12-20 4:56 ` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions Alistair Francis
2021-12-20 4:56 ` [PULL 29/88] target/riscv: rvv-1.0: index " Alistair Francis
2021-12-20 4:56 ` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load Alistair Francis
2021-12-20 4:56 ` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions Alistair Francis
2021-12-20 4:56 ` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Alistair Francis
2021-12-20 4:56 ` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction Alistair Francis
2021-12-20 4:56 ` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions Alistair Francis
2021-12-20 4:56 ` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction Alistair Francis
2021-12-20 4:56 ` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction Alistair Francis
2021-12-20 4:56 ` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions Alistair Francis
2021-12-20 4:56 ` [PULL 40/88] target/riscv: rvv-1.0: iota instruction Alistair Francis
2021-12-20 4:56 ` [PULL 41/88] target/riscv: rvv-1.0: element index instruction Alistair Francis
2021-12-20 4:56 ` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended Alistair Francis
2021-12-20 4:56 ` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions Alistair Francis
2021-12-20 4:56 ` Alistair Francis [this message]
2021-12-20 4:56 ` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction Alistair Francis
2021-12-20 4:56 ` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 47/88] target/riscv: rvv-1.0: whole register " Alistair Francis
2021-12-20 4:56 ` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions Alistair Francis
2021-12-20 4:56 ` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow Alistair Francis
2021-12-20 4:56 ` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions Alistair Francis
2021-12-20 4:56 ` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions Alistair Francis
2021-12-20 4:56 ` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions Alistair Francis
2021-12-20 4:56 ` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions Alistair Francis
2021-12-20 4:56 ` [PULL 58/88] target/riscv: rvv-1.0: slide instructions Alistair Francis
2021-12-20 4:56 ` [PULL 59/88] target/riscv: rvv-1.0: floating-point " Alistair Francis
2021-12-20 4:56 ` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Alistair Francis
2021-12-20 4:56 ` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction Alistair Francis
2021-12-20 4:56 ` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions Alistair Francis
2021-12-20 4:56 ` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Alistair Francis
2021-12-20 4:56 ` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Alistair Francis
2021-12-20 4:56 ` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction Alistair Francis
2021-12-20 4:56 ` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions Alistair Francis
2021-12-20 4:56 ` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum Alistair Francis
2021-12-20 4:56 ` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Alistair Francis
2021-12-20 4:56 ` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function Alistair Francis
2021-12-20 4:56 ` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Alistair Francis
2021-12-20 4:56 ` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR Alistair Francis
2021-12-20 4:56 ` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Alistair Francis
2021-12-20 4:56 ` [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32 Alistair Francis
2021-12-20 4:56 ` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Alistair Francis
2021-12-20 4:56 ` [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal " Alistair Francis
2021-12-20 4:56 ` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Alistair Francis
2021-12-20 4:56 ` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction Alistair Francis
2021-12-20 4:56 ` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Alistair Francis
2021-12-20 4:56 ` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Alistair Francis
2021-12-20 4:57 ` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Alistair Francis
2021-12-20 4:57 ` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment Alistair Francis
2021-12-20 4:57 ` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions Alistair Francis
2021-12-20 4:57 ` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32 Alistair Francis via
2021-12-20 4:57 ` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions Alistair Francis
2021-12-20 4:57 ` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr Alistair Francis
2021-12-20 21:19 ` [PULL 00/88] riscv-to-apply queue Richard Henderson
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