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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-52-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/vector_helper.c | 141 ++++++++++++++++-------- target/riscv/insn_trans/trans_rvv.c.inc | 16 +++ 4 files changed, 121 insertions(+), 45 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 304c12494d..012d034377 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1071,6 +1071,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl,= ptr, env, i32) DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 +DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32) + DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7548b71efd..c5cc14c45c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -577,6 +577,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 101011= 1 @r_vm vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d79f59e443..7fa5189af4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4455,57 +4455,108 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t= , H2) GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) =20 -#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) = \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, = \ - CPURISCVState *env, uint32_t desc) = \ -{ = \ - uint32_t vm =3D vext_vm(desc); = \ - uint32_t vl =3D env->vl; = \ - uint32_t i; = \ - = \ - for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, i)) { = \ - continue; = \ - } = \ - if (i =3D=3D 0) { = \ - *((ETYPE *)vd + H(i)) =3D s1; = \ - } else { = \ - *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ - } = \ - } = \ +#define GEN_VEXT_VSLIE1UP(ESZ, H) = \ +static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *v= s2, \ + CPURISCVState *env, uint32_t desc) = \ +{ = \ + typedef uint##ESZ##_t ETYPE; = \ + uint32_t vm =3D vext_vm(desc); = \ + uint32_t vl =3D env->vl; = \ + uint32_t i; = \ + = \ + for (i =3D 0; i < vl; i++) { = \ + if (!vm && !vext_elem_mask(v0, i)) { = \ + continue; = \ + } = \ + if (i =3D=3D 0) { = \ + *((ETYPE *)vd + H(i)) =3D s1; = \ + } else { = \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - 1)); = \ + } = \ + } = \ +} + +GEN_VEXT_VSLIE1UP(8, H1) +GEN_VEXT_VSLIE1UP(16, H2) +GEN_VEXT_VSLIE1UP(32, H4) +GEN_VEXT_VSLIE1UP(64, H8) + +#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ } =20 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=3Dx[rs1], vd[i+1] =3D vs2[i] */ -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8) - -#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) = \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, = \ - CPURISCVState *env, uint32_t desc) = \ -{ = \ - uint32_t vm =3D vext_vm(desc); = \ - uint32_t vl =3D env->vl; = \ - uint32_t i; = \ - = \ - for (i =3D 0; i < vl; i++) { = \ - if (!vm && !vext_elem_mask(v0, i)) { = \ - continue; = \ - } = \ - if (i =3D=3D vl - 1) { = \ - *((ETYPE *)vd + H(i)) =3D s1; = \ - } else { = \ - *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ - } = \ - } = \ +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, 8) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) + +#define GEN_VEXT_VSLIDE1DOWN(ESZ, H) = \ +static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void = *vs2, \ + CPURISCVState *env, uint32_t desc) = \ +{ = \ + typedef uint##ESZ##_t ETYPE; = \ + uint32_t vm =3D vext_vm(desc); = \ + uint32_t vl =3D env->vl; = \ + uint32_t i; = \ + = \ + for (i =3D 0; i < vl; i++) { = \ + if (!vm && !vext_elem_mask(v0, i)) { = \ + continue; = \ + } = \ + if (i =3D=3D vl - 1) { = \ + *((ETYPE *)vd + H(i)) =3D s1; = \ + } else { = \ + *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i + 1)); = \ + } = \ + } = \ +} + +GEN_VEXT_VSLIDE1DOWN(8, H1) +GEN_VEXT_VSLIDE1DOWN(16, H2) +GEN_VEXT_VSLIDE1DOWN(32, H4) +GEN_VEXT_VSLIDE1DOWN(64, H8) + +#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ } =20 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+1], vd[vl-1]=3Dx[rs= 1] */ -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, 8) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, 16) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64) + +/* Vector Floating-Point Slide Instructions */ +#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=3Df[rs1], vd[i+1] =3D vs2[i] *= / +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64) + +#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] =3D vs2[i+1], vd[vl-1]=3Df[r= s1] */ +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, 16) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, 32) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64) =20 /* Vector Register Gather Instruction */ #define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) = \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_= trans/trans_rvv.c.inc index 5c0c3d2547..597a367444 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3121,6 +3121,22 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) =20 +/* Vector Floating-Point Slide Instructions */ +static bool fslideup_check(DisasContext *s, arg_rmrr *a) +{ + return slideup_check(s, a) && + require_rvf(s); +} + +static bool fslidedown_check(DisasContext *s, arg_rmrr *a) +{ + return slidedown_check(s, a) && + require_rvf(s); +} + +GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check) +GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check) + /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { --=20 2.31.1