From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Hsiangkai Wang <kai.wang@sifive.com>,
Greentime Hu <greentime.hu@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32
Date: Mon, 20 Dec 2021 14:56:53 +1000 [thread overview]
Message-ID: <20211220045705.62174-77-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com>
From: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 2 +
target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 187 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5d93ccdfa7..dc10f27093 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -291,6 +291,7 @@ struct RISCVCPU {
CPURISCVState env;
char *dyn_csr_xml;
+ char *dyn_vreg_xml;
/* Configuration Settings */
struct {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 728092f78c..9776297c79 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -675,6 +675,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
if (strcmp(xmlname, "riscv-csr.xml") == 0) {
return cpu->dyn_csr_xml;
+ } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
+ return cpu->dyn_vreg_xml;
}
return NULL;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..881ab33392 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,32 @@
#include "exec/gdbstub.h"
#include "cpu.h"
+struct TypeSize {
+ const char *gdb_type;
+ const char *id;
+ int size;
+ const char suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+ /* quads */
+ { "uint128", "quads", 128, 'q' },
+ /* 64 bit */
+ { "uint64", "longs", 64, 'l' },
+ /* 32 bit */
+ { "uint32", "words", 32, 'w' },
+ /* 16 bit */
+ { "uint16", "shorts", 16, 's' },
+ /*
+ * TODO: currently there is no reliable way of telling
+ * if the remote gdb actually understands ieee_half so
+ * we don't expose it in the target description for now.
+ * { "ieee_half", 16, 'h', 'f' },
+ */
+ /* bytes */
+ { "uint8", "bytes", 8, 'b' },
+};
+
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
+/*
+ * Convert register index number passed by GDB to the correspond
+ * vector CSR number. Vector CSRs are defined after vector registers
+ * in dynamic generated riscv-vector.xml, thus the starting register index
+ * of vector CSRs is 32.
+ * Return 0 if register index number is out of range.
+ */
+static int riscv_gdb_vector_csrno(int num_regs)
+{
+ /*
+ * The order of vector CSRs in the switch case
+ * should match with the order defined in csr_ops[].
+ */
+ switch (num_regs) {
+ case 32:
+ return CSR_VSTART;
+ case 33:
+ return CSR_VXSAT;
+ case 34:
+ return CSR_VXRM;
+ case 35:
+ return CSR_VCSR;
+ case 36:
+ return CSR_VL;
+ case 37:
+ return CSR_VTYPE;
+ case 38:
+ return CSR_VLENB;
+ default:
+ /* Unknown register. */
+ return 0;
+ }
+}
+
+static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ int cnt = 0;
+ for (i = 0; i < vlenb; i += 8) {
+ cnt += gdb_get_reg64(buf,
+ env->vreg[(n * vlenb + i) / 8]);
+ }
+ return cnt;
+ }
+
+ int csrno = riscv_gdb_vector_csrno(n);
+
+ if (!csrno) {
+ return 0;
+ }
+
+ target_ulong val = 0;
+ int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+ if (result == 0) {
+ return gdb_get_regl(buf, val);
+ }
+
+ return 0;
+}
+
+static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ for (i = 0; i < vlenb; i += 8) {
+ env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
+ }
+ return vlenb;
+ }
+
+ int csrno = riscv_gdb_vector_csrno(n);
+
+ if (!csrno) {
+ return 0;
+ }
+
+ target_ulong val = ldtul_p(mem_buf);
+ int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
+
+ if (result == 0) {
+ return sizeof(target_ulong);
+ }
+
+ return 0;
+}
+
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < CSR_TABLE_SIZE) {
@@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
return CSR_TABLE_SIZE;
}
+static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ GString *s = g_string_new(NULL);
+ g_autoptr(GString) ts = g_string_new("");
+ int reg_width = cpu->cfg.vlen;
+ int num_regs = 0;
+ int i;
+
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">");
+
+ /* First define types and totals in a whole VL */
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ int count = reg_width / vec_lanes[i].size;
+ g_string_printf(ts, "%s", vec_lanes[i].id);
+ g_string_append_printf(s,
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+ ts->str, vec_lanes[i].gdb_type, count);
+ }
+
+ /* Define unions */
+ g_string_append_printf(s, "<union id=\"riscv_vector\">");
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>",
+ vec_lanes[i].suffix,
+ vec_lanes[i].id);
+ }
+ g_string_append(s, "</union>");
+
+ /* Define vector registers */
+ for (i = 0; i < 32; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"v%d\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"riscv_vector\"/>",
+ i, reg_width, base_reg++);
+ num_regs++;
+ }
+
+ /* Define vector CSRs */
+ const char *vector_csrs[7] = {
+ "vstart", "vxsat", "vxrm", "vcsr",
+ "vl", "vtype", "vlenb"
+ };
+
+ for (i = 0; i < 7; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"%s\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"int\"/>",
+ vector_csrs[i], TARGET_LONG_BITS, base_reg++);
+ num_regs++;
+ }
+
+ g_string_append_printf(s, "</feature>");
+
+ cpu->dyn_vreg_xml = g_string_free(s, false);
+ return num_regs;
+}
+
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
+ if (env->misa_ext & RVV) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
+ ricsv_gen_dynamic_vector_xml(cs,
+ cs->gdb_num_regs),
+ "riscv-vector.xml", 0);
+ }
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
--
2.31.1
next prev parent reply other threads:[~2021-12-20 6:07 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 4:55 [PULL 00/88] riscv-to-apply queue Alistair Francis
2021-12-20 4:55 ` [PULL 01/88] target/riscv: zfh: half-precision load and store Alistair Francis
2021-12-20 4:55 ` [PULL 02/88] target/riscv: zfh: half-precision computational Alistair Francis
2021-12-20 4:55 ` [PULL 03/88] target/riscv: zfh: half-precision convert and move Alistair Francis
2021-12-20 4:55 ` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare Alistair Francis
2021-12-20 4:55 ` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify Alistair Francis
2021-12-20 4:55 ` [PULL 06/88] target/riscv: zfh: add Zfh cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 07/88] target/riscv: zfh: implement zfhmin extension Alistair Francis
2021-12-20 4:55 ` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support Alistair Francis
2021-12-20 4:55 ` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field Alistair Francis
2021-12-20 4:55 ` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Alistair Francis
2021-12-20 4:55 ` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field Alistair Francis
2021-12-20 4:55 ` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status Alistair Francis
2021-12-20 4:55 ` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers Alistair Francis
2021-12-20 4:55 ` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register Alistair Francis
2021-12-20 4:55 ` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register Alistair Francis
2021-12-20 4:55 ` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers Alistair Francis
2021-12-20 4:55 ` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations Alistair Francis
2021-12-20 4:55 ` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL Alistair Francis
2021-12-20 4:55 ` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA Alistair Francis
2021-12-20 4:56 ` [PULL 23/88] target/riscv: rvv-1.0: update check functions Alistair Francis
2021-12-20 4:56 ` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions Alistair Francis
2021-12-20 4:56 ` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function Alistair Francis
2021-12-20 4:56 ` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions Alistair Francis
2021-12-20 4:56 ` [PULL 27/88] target/riscv: rvv-1.0: configure instructions Alistair Francis
2021-12-20 4:56 ` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions Alistair Francis
2021-12-20 4:56 ` [PULL 29/88] target/riscv: rvv-1.0: index " Alistair Francis
2021-12-20 4:56 ` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load Alistair Francis
2021-12-20 4:56 ` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions Alistair Francis
2021-12-20 4:56 ` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Alistair Francis
2021-12-20 4:56 ` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction Alistair Francis
2021-12-20 4:56 ` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions Alistair Francis
2021-12-20 4:56 ` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction Alistair Francis
2021-12-20 4:56 ` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction Alistair Francis
2021-12-20 4:56 ` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions Alistair Francis
2021-12-20 4:56 ` [PULL 40/88] target/riscv: rvv-1.0: iota instruction Alistair Francis
2021-12-20 4:56 ` [PULL 41/88] target/riscv: rvv-1.0: element index instruction Alistair Francis
2021-12-20 4:56 ` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended Alistair Francis
2021-12-20 4:56 ` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions Alistair Francis
2021-12-20 4:56 ` [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction Alistair Francis
2021-12-20 4:56 ` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 47/88] target/riscv: rvv-1.0: whole register " Alistair Francis
2021-12-20 4:56 ` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions Alistair Francis
2021-12-20 4:56 ` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow Alistair Francis
2021-12-20 4:56 ` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions Alistair Francis
2021-12-20 4:56 ` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions Alistair Francis
2021-12-20 4:56 ` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions Alistair Francis
2021-12-20 4:56 ` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions Alistair Francis
2021-12-20 4:56 ` [PULL 58/88] target/riscv: rvv-1.0: slide instructions Alistair Francis
2021-12-20 4:56 ` [PULL 59/88] target/riscv: rvv-1.0: floating-point " Alistair Francis
2021-12-20 4:56 ` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Alistair Francis
2021-12-20 4:56 ` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction Alistair Francis
2021-12-20 4:56 ` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions Alistair Francis
2021-12-20 4:56 ` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Alistair Francis
2021-12-20 4:56 ` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Alistair Francis
2021-12-20 4:56 ` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction Alistair Francis
2021-12-20 4:56 ` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions Alistair Francis
2021-12-20 4:56 ` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum Alistair Francis
2021-12-20 4:56 ` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Alistair Francis
2021-12-20 4:56 ` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function Alistair Francis
2021-12-20 4:56 ` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Alistair Francis
2021-12-20 4:56 ` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR Alistair Francis
2021-12-20 4:56 ` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Alistair Francis
2021-12-20 4:56 ` Alistair Francis [this message]
2021-12-20 4:56 ` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Alistair Francis
2021-12-20 4:56 ` [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal " Alistair Francis
2021-12-20 4:56 ` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Alistair Francis
2021-12-20 4:56 ` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction Alistair Francis
2021-12-20 4:56 ` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Alistair Francis
2021-12-20 4:56 ` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Alistair Francis
2021-12-20 4:57 ` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Alistair Francis
2021-12-20 4:57 ` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment Alistair Francis
2021-12-20 4:57 ` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions Alistair Francis
2021-12-20 4:57 ` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32 Alistair Francis via
2021-12-20 4:57 ` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions Alistair Francis
2021-12-20 4:57 ` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr Alistair Francis
2021-12-20 21:19 ` [PULL 00/88] riscv-to-apply queue Richard Henderson
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