From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 78/88] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Date: Mon, 20 Dec 2021 14:56:55 +1000 [thread overview]
Message-ID: <20211220045705.62174-79-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211220045705.62174-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-71-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/vector_helper.c | 191 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
4 files changed, 197 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index bdf06dfb24..ab283d12b7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -845,6 +845,10 @@ DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32)
+
DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e5f288943..952768f8de 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -561,6 +561,7 @@ vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
+vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d5f3229bcb..946dca53ff 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3587,6 +3587,197 @@ GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
+/*
+ * Vector Floating-Point Reciprocal Estimate Instruction
+ *
+ * Adapted from riscv-v-spec recip.c:
+ * https://github.com/riscv/riscv-v-spec/blob/master/recip.c
+ */
+static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
+ float_status *s)
+{
+ uint64_t sign = extract64(f, frac_size + exp_size, 1);
+ uint64_t exp = extract64(f, frac_size, exp_size);
+ uint64_t frac = extract64(f, 0, frac_size);
+
+ const uint8_t lookup_table[] = {
+ 127, 125, 123, 121, 119, 117, 116, 114,
+ 112, 110, 109, 107, 105, 104, 102, 100,
+ 99, 97, 96, 94, 93, 91, 90, 88,
+ 87, 85, 84, 83, 81, 80, 79, 77,
+ 76, 75, 74, 72, 71, 70, 69, 68,
+ 66, 65, 64, 63, 62, 61, 60, 59,
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 40, 40, 39, 38, 37, 36,
+ 35, 35, 34, 33, 32, 31, 31, 30,
+ 29, 28, 28, 27, 26, 25, 25, 24,
+ 23, 23, 22, 21, 21, 20, 19, 19,
+ 18, 17, 17, 16, 15, 15, 14, 14,
+ 13, 12, 12, 11, 11, 10, 9, 9,
+ 8, 8, 7, 7, 6, 5, 5, 4,
+ 4, 3, 3, 2, 2, 1, 1, 0
+ };
+ const int precision = 7;
+
+ if (exp == 0 && frac != 0) { /* subnormal */
+ /* Normalize the subnormal. */
+ while (extract64(frac, frac_size - 1, 1) == 0) {
+ exp--;
+ frac <<= 1;
+ }
+
+ frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
+
+ if (exp != 0 && exp != UINT64_MAX) {
+ /*
+ * Overflow to inf or max value of same sign,
+ * depending on sign and rounding mode.
+ */
+ s->float_exception_flags |= (float_flag_inexact |
+ float_flag_overflow);
+
+ if ((s->float_rounding_mode == float_round_to_zero) ||
+ ((s->float_rounding_mode == float_round_down) && !sign) ||
+ ((s->float_rounding_mode == float_round_up) && sign)) {
+ /* Return greatest/negative finite value. */
+ return (sign << (exp_size + frac_size)) |
+ (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
+ } else {
+ /* Return +-inf. */
+ return (sign << (exp_size + frac_size)) |
+ MAKE_64BIT_MASK(frac_size, exp_size);
+ }
+ }
+ }
+
+ int idx = frac >> (frac_size - precision);
+ uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
+ (frac_size - precision);
+ uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
+
+ if (out_exp == 0 || out_exp == UINT64_MAX) {
+ /*
+ * The result is subnormal, but don't raise the underflow exception,
+ * because there's no additional loss of precision.
+ */
+ out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1);
+ if (out_exp == UINT64_MAX) {
+ out_frac >>= 1;
+ out_exp = 0;
+ }
+ }
+
+ uint64_t val = 0;
+ val = deposit64(val, 0, frac_size, out_frac);
+ val = deposit64(val, frac_size, exp_size, out_exp);
+ val = deposit64(val, frac_size + exp_size, 1, sign);
+ return val;
+}
+
+static float16 frec7_h(float16 f, float_status *s)
+{
+ int exp_size = 5, frac_size = 10;
+ bool sign = float16_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float16_is_infinity(f)) {
+ return float16_set_sign(float16_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float16_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float16_set_sign(float16_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float16_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float16_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float16_is_quiet_nan(f, s)) {
+ return float16_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float16(val);
+}
+
+static float32 frec7_s(float32 f, float_status *s)
+{
+ int exp_size = 8, frac_size = 23;
+ bool sign = float32_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float32_is_infinity(f)) {
+ return float32_set_sign(float32_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float32_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float32_set_sign(float32_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float32_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float32_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float32_is_quiet_nan(f, s)) {
+ return float32_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float32(val);
+}
+
+static float64 frec7_d(float64 f, float_status *s)
+{
+ int exp_size = 11, frac_size = 52;
+ bool sign = float64_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float64_is_infinity(f)) {
+ return float64_set_sign(float64_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float64_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float64_set_sign(float64_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float64_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float64_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float64_is_quiet_nan(f, s)) {
+ return float64_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float64(val);
+}
+
+RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
+RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
+RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
+GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
+
/* Vector Floating-Point MIN/MAX Instructions */
RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number)
RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8fe718610a..ff8f6df8f7 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2408,6 +2408,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
+GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point MIN/MAX Instructions */
GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
--
2.31.1
next prev parent reply other threads:[~2021-12-20 6:12 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-20 4:55 [PULL 00/88] riscv-to-apply queue Alistair Francis
2021-12-20 4:55 ` [PULL 01/88] target/riscv: zfh: half-precision load and store Alistair Francis
2021-12-20 4:55 ` [PULL 02/88] target/riscv: zfh: half-precision computational Alistair Francis
2021-12-20 4:55 ` [PULL 03/88] target/riscv: zfh: half-precision convert and move Alistair Francis
2021-12-20 4:55 ` [PULL 04/88] target/riscv: zfh: half-precision floating-point compare Alistair Francis
2021-12-20 4:55 ` [PULL 05/88] target/riscv: zfh: half-precision floating-point classify Alistair Francis
2021-12-20 4:55 ` [PULL 06/88] target/riscv: zfh: add Zfh cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 07/88] target/riscv: zfh: implement zfhmin extension Alistair Francis
2021-12-20 4:55 ` [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property Alistair Francis
2021-12-20 4:55 ` [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support Alistair Francis
2021-12-20 4:55 ` [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field Alistair Francis
2021-12-20 4:55 ` [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Alistair Francis
2021-12-20 4:55 ` [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field Alistair Francis
2021-12-20 4:55 ` [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field Alistair Francis
2021-12-20 4:55 ` [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status Alistair Francis
2021-12-20 4:55 ` [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers Alistair Francis
2021-12-20 4:55 ` [PULL 17/88] target/riscv: rvv-1.0: add vcsr register Alistair Francis
2021-12-20 4:55 ` [PULL 18/88] target/riscv: rvv-1.0: add vlenb register Alistair Francis
2021-12-20 4:55 ` [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers Alistair Francis
2021-12-20 4:55 ` [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations Alistair Francis
2021-12-20 4:55 ` [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL Alistair Francis
2021-12-20 4:55 ` [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA Alistair Francis
2021-12-20 4:56 ` [PULL 23/88] target/riscv: rvv-1.0: update check functions Alistair Francis
2021-12-20 4:56 ` [PULL 24/88] target/riscv: introduce more imm value modes in translator functions Alistair Francis
2021-12-20 4:56 ` [PULL 25/88] target/riscv: rvv:1.0: add translation-time nan-box helper function Alistair Francis
2021-12-20 4:56 ` [PULL 26/88] target/riscv: rvv-1.0: remove amo operations instructions Alistair Francis
2021-12-20 4:56 ` [PULL 27/88] target/riscv: rvv-1.0: configure instructions Alistair Francis
2021-12-20 4:56 ` [PULL 28/88] target/riscv: rvv-1.0: stride load and store instructions Alistair Francis
2021-12-20 4:56 ` [PULL 29/88] target/riscv: rvv-1.0: index " Alistair Francis
2021-12-20 4:56 ` [PULL 30/88] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 31/88] target/riscv: rvv-1.0: fault-only-first unit stride load Alistair Francis
2021-12-20 4:56 ` [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions Alistair Francis
2021-12-20 4:56 ` [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Alistair Francis
2021-12-20 4:56 ` [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Alistair Francis
2021-12-20 4:56 ` [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction Alistair Francis
2021-12-20 4:56 ` [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions Alistair Francis
2021-12-20 4:56 ` [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction Alistair Francis
2021-12-20 4:56 ` [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction Alistair Francis
2021-12-20 4:56 ` [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions Alistair Francis
2021-12-20 4:56 ` [PULL 40/88] target/riscv: rvv-1.0: iota instruction Alistair Francis
2021-12-20 4:56 ` [PULL 41/88] target/riscv: rvv-1.0: element index instruction Alistair Francis
2021-12-20 4:56 ` [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended Alistair Francis
2021-12-20 4:56 ` [PULL 43/88] target/riscv: rvv-1.0: register gather instructions Alistair Francis
2021-12-20 4:56 ` [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction Alistair Francis
2021-12-20 4:56 ` [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions Alistair Francis
2021-12-20 4:56 ` [PULL 47/88] target/riscv: rvv-1.0: whole register " Alistair Francis
2021-12-20 4:56 ` [PULL 48/88] target/riscv: rvv-1.0: integer extension instructions Alistair Francis
2021-12-20 4:56 ` [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow Alistair Francis
2021-12-20 4:56 ` [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions Alistair Francis
2021-12-20 4:56 ` [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Alistair Francis
2021-12-20 4:56 ` [PULL 55/88] target/riscv: rvv-1.0: integer comparison instructions Alistair Francis
2021-12-20 4:56 ` [PULL 56/88] target/riscv: rvv-1.0: floating-point compare instructions Alistair Francis
2021-12-20 4:56 ` [PULL 57/88] target/riscv: rvv-1.0: mask-register logical instructions Alistair Francis
2021-12-20 4:56 ` [PULL 58/88] target/riscv: rvv-1.0: slide instructions Alistair Francis
2021-12-20 4:56 ` [PULL 59/88] target/riscv: rvv-1.0: floating-point " Alistair Francis
2021-12-20 4:56 ` [PULL 60/88] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Alistair Francis
2021-12-20 4:56 ` [PULL 61/88] target/riscv: rvv-1.0: single-width floating-point reduction Alistair Francis
2021-12-20 4:56 ` [PULL 62/88] target/riscv: rvv-1.0: widening floating-point reduction instructions Alistair Francis
2021-12-20 4:56 ` [PULL 63/88] target/riscv: rvv-1.0: single-width scaling shift instructions Alistair Francis
2021-12-20 4:56 ` [PULL 64/88] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Alistair Francis
2021-12-20 4:56 ` [PULL 65/88] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Alistair Francis
2021-12-20 4:56 ` [PULL 66/88] target/riscv: rvv-1.0: remove integer extract instruction Alistair Francis
2021-12-20 4:56 ` [PULL 67/88] target/riscv: rvv-1.0: floating-point min/max instructions Alistair Francis
2021-12-20 4:56 ` [PULL 68/88] target/riscv: introduce floating-point rounding mode enum Alistair Francis
2021-12-20 4:56 ` [PULL 69/88] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Alistair Francis
2021-12-20 4:56 ` [PULL 70/88] target/riscv: rvv-1.0: widening floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 71/88] target/riscv: add "set round to odd" rounding mode helper function Alistair Francis
2021-12-20 4:56 ` [PULL 72/88] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Alistair Francis
2021-12-20 4:56 ` [PULL 73/88] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Alistair Francis
2021-12-20 4:56 ` [PULL 74/88] target/riscv: rvv-1.0: implement vstart CSR Alistair Francis
2021-12-20 4:56 ` [PULL 75/88] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Alistair Francis
2021-12-20 4:56 ` [PULL 76/88] target/riscv: gdb: support vector registers for rv64 & rv32 Alistair Francis
2021-12-20 4:56 ` [PULL 77/88] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Alistair Francis
2021-12-20 4:56 ` Alistair Francis [this message]
2021-12-20 4:56 ` [PULL 79/88] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Alistair Francis
2021-12-20 4:56 ` [PULL 80/88] target/riscv: rvv-1.0: add vsetivli instruction Alistair Francis
2021-12-20 4:56 ` [PULL 81/88] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Alistair Francis
2021-12-20 4:56 ` [PULL 82/88] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Alistair Francis
2021-12-20 4:57 ` [PULL 83/88] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Alistair Francis
2021-12-20 4:57 ` [PULL 84/88] target/riscv: rvv-1.0: update opivv_vadc_check() comment Alistair Francis
2021-12-20 4:57 ` [PULL 85/88] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions Alistair Francis
2021-12-20 4:57 ` [PULL 86/88] riscv: Set 5.4 as minimum kernel version for riscv32 Alistair Francis via
2021-12-20 4:57 ` [PULL 87/88] target/riscv: Enable bitmanip Zb[abcs] instructions Alistair Francis
2021-12-20 4:57 ` [PULL 88/88] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr Alistair Francis
2021-12-20 21:19 ` [PULL 00/88] riscv-to-apply queue Richard Henderson
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