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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) =3D ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 946dca53ff..83373ca6fc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -279,15 +279,15 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t d= esc, - vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uintptr_t ra, MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl, + uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, esz); =20 /* load bytes from guest memory */ - for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { + for (i =3D env->vstart; i < evl; i++, env->vstart++) { k =3D 0; while (k < nf) { target_ulong addr =3D base + ((i * nf + k) << esz); @@ -316,7 +316,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong ba= se, \ CPURISCVState *env, uint32_t desc) = \ { = \ vext_ldst_us(vd, base, env, desc, LOAD_FN, = \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); = \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); = \ } =20 GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) @@ -324,20 +324,20 @@ GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) =20 -#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) = \ -void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, = \ - CPURISCVState *env, uint32_t desc) = \ -{ = \ - uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); = \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, = \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); = \ -} = \ - = \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, = \ - CPURISCVState *env, uint32_t desc) = \ -{ = \ - vext_ldst_us(vd, base, env, desc, STORE_FN, = \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); = \ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) = \ +void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, = \ + CPURISCVState *env, uint32_t desc) = \ +{ = \ + uint32_t stride =3D vext_nf(desc) << ctzl(sizeof(ETYPE)); = \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, = \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); = \ +} = \ + = \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, = \ + CPURISCVState *env, uint32_t desc) = \ +{ = \ + vext_ldst_us(vd, base, env, desc, STORE_FN, = \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE);= \ } =20 GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) --=20 2.31.1