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envelope-from=prvs=9816edf2f=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers. The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value on an illegal instruction. This doesn't match all CPUs (some CPUs won't write the data), but in QEMU let's just populate the value on illegal instructions. This won't break any guest software, but will provide more information to guests. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..3a163b57ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -127,6 +127,8 @@ struct CPURISCVState { target_ulong frm; =20 target_ulong badaddr; + uint32_t bins; + target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9e1f5ee177..f76ba834e6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1007,6 +1007,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) write_gva =3D true; tval =3D env->badaddr; break; + case RISCV_EXCP_ILLEGAL_INST: + tval =3D env->bins; + break; default: break; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 24251bc8cc..921ca06bf9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -167,6 +167,9 @@ static void generate_exception_mtval(DisasContext *ct= x, int excp) =20 static void gen_exception_illegal(DisasContext *ctx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } =20 --=20 2.31.1