From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"XiaoJuan Yang" <yangxiaojuan@loongson.cn>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"WANG Xuerui" <git@xen0n.name>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Song Gao" <gaosong@loongson.cn>
Subject: [PATCH v11 13/31] tcg/loongarch64: Implement deposit/extract ops
Date: Tue, 21 Dec 2021 13:40:47 +0800 [thread overview]
Message-ID: <20211221054105.178795-14-git@xen0n.name> (raw)
In-Reply-To: <20211221054105.178795-1-git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 21 +++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 8 ++++----
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 9ac24b8ad0..d958183020 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -18,3 +18,4 @@ C_O0_I1(r)
C_O1_I1(r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, rU)
+C_O1_I2(r, 0, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index d9508d5295..9eba8f8146 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -531,6 +531,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_extract_i32:
+ tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
+ break;
+ case INDEX_op_extract_i64:
+ tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
+ break;
+
+ case INDEX_op_deposit_i32:
+ tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
+ break;
+ case INDEX_op_deposit_i64:
+ tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -560,6 +574,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_ext_i32_i64:
case INDEX_op_not_i32:
case INDEX_op_not_i64:
+ case INDEX_op_extract_i32:
+ case INDEX_op_extract_i64:
return C_O1_I1(r, r);
case INDEX_op_andc_i32:
@@ -584,6 +600,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
/* LoongArch reg-imm bitops have their imms ZERO-extended */
return C_O1_I2(r, r, rU);
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ /* Must deposit into the same register as input */
+ return C_O1_I2(r, 0, rZ);
+
default:
g_assert_not_reached();
}
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index cc9aecc681..1c9d0a9988 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -97,8 +97,8 @@ typedef enum {
#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 0
-#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_extract_i32 0
+#define TCG_TARGET_HAS_deposit_i32 1
+#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 0
@@ -134,8 +134,8 @@ typedef enum {
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 0
-#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_extract_i64 0
+#define TCG_TARGET_HAS_deposit_i64 1
+#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extrl_i64_i32 1
--
2.34.0
next prev parent reply other threads:[~2021-12-21 5:53 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 5:40 [PATCH v11 00/31] LoongArch64 port of QEMU TCG WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 01/31] elf: Add machine type value for LoongArch WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 02/31] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 03/31] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 06/31] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 07/31] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 08/31] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 10/31] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 11/31] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-12-21 5:40 ` WANG Xuerui [this message]
2021-12-21 5:40 ` [PATCH v11 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 15/31] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 17/31] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 19/31] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 20/31] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 21/31] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 22/31] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-12-21 5:40 ` [PATCH v11 25/31] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-12-21 5:41 ` [PATCH v11 26/31] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-12-21 5:41 ` [PATCH v11 27/31] tcg/loongarch64: Register the JIT WANG Xuerui
2021-12-21 5:41 ` [PATCH v11 28/31] common-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-12-21 5:41 ` [PATCH v11 29/31] linux-user: Implement CPU-specific signal handler " WANG Xuerui
2021-12-30 3:11 ` gaosong
2021-12-30 3:50 ` WANG Xuerui
2022-01-04 12:48 ` Philippe Mathieu-Daudé
2021-12-21 5:41 ` [PATCH v11 30/31] configure, meson.build: Mark support " WANG Xuerui
2021-12-21 5:41 ` [PATCH v11 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab WANG Xuerui
2021-12-21 8:44 ` [PATCH v11 00/31] LoongArch64 port of QEMU TCG Philippe Mathieu-Daudé
2021-12-21 9:36 ` gaosong
2021-12-21 12:00 ` Philippe Mathieu-Daudé
2021-12-23 2:00 ` gaosong
2021-12-21 16:49 ` Richard Henderson
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