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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 11/31] tcg/loongarch64: Implement sign-/zero-extension ops
Date: Tue, 21 Dec 2021 08:47:17 -0800	[thread overview]
Message-ID: <20211221164737.1076007-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211221164737.1076007-1-richard.henderson@linaro.org>

From: WANG Xuerui <git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-12-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target-con-set.h |  1 +
 tcg/loongarch64/tcg-target.h         | 24 ++++----
 tcg/loongarch64/tcg-target.c.inc     | 82 ++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+), 12 deletions(-)

diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 5cc4407367..7e459490ea 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -15,3 +15,4 @@
  * tcg-target-con-str.h; the constraint combination is inclusive or.
  */
 C_O0_I1(r)
+C_O1_I1(r, r)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 25328646f0..a6d9e036fc 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -107,10 +107,10 @@ typedef enum {
 #define TCG_TARGET_HAS_muls2_i32        0
 #define TCG_TARGET_HAS_muluh_i32        0
 #define TCG_TARGET_HAS_mulsh_i32        0
-#define TCG_TARGET_HAS_ext8s_i32        0
-#define TCG_TARGET_HAS_ext16s_i32       0
-#define TCG_TARGET_HAS_ext8u_i32        0
-#define TCG_TARGET_HAS_ext16u_i32       0
+#define TCG_TARGET_HAS_ext8s_i32        1
+#define TCG_TARGET_HAS_ext16s_i32       1
+#define TCG_TARGET_HAS_ext8u_i32        1
+#define TCG_TARGET_HAS_ext16u_i32       1
 #define TCG_TARGET_HAS_bswap16_i32      0
 #define TCG_TARGET_HAS_bswap32_i32      0
 #define TCG_TARGET_HAS_not_i32          0
@@ -138,14 +138,14 @@ typedef enum {
 #define TCG_TARGET_HAS_extract_i64      0
 #define TCG_TARGET_HAS_sextract_i64     0
 #define TCG_TARGET_HAS_extract2_i64     0
-#define TCG_TARGET_HAS_extrl_i64_i32    0
-#define TCG_TARGET_HAS_extrh_i64_i32    0
-#define TCG_TARGET_HAS_ext8s_i64        0
-#define TCG_TARGET_HAS_ext16s_i64       0
-#define TCG_TARGET_HAS_ext32s_i64       0
-#define TCG_TARGET_HAS_ext8u_i64        0
-#define TCG_TARGET_HAS_ext16u_i64       0
-#define TCG_TARGET_HAS_ext32u_i64       0
+#define TCG_TARGET_HAS_extrl_i64_i32    1
+#define TCG_TARGET_HAS_extrh_i64_i32    1
+#define TCG_TARGET_HAS_ext8s_i64        1
+#define TCG_TARGET_HAS_ext16s_i64       1
+#define TCG_TARGET_HAS_ext32s_i64       1
+#define TCG_TARGET_HAS_ext8u_i64        1
+#define TCG_TARGET_HAS_ext16u_i64       1
+#define TCG_TARGET_HAS_ext32u_i64       1
 #define TCG_TARGET_HAS_bswap16_i64      0
 #define TCG_TARGET_HAS_bswap32_i64      0
 #define TCG_TARGET_HAS_bswap64_i64      0
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 3a8c52465b..25b58c7828 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -382,6 +382,36 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
     }
 }
 
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_andi(s, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_sext_b(s, ret, arg);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_sext_h(s, ret, arg);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+    tcg_out_opc_addi_w(s, ret, arg, 0);
+}
+
 /*
  * Entry-points
  */
@@ -391,6 +421,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
                        const int const_args[TCG_MAX_OP_ARGS])
 {
     TCGArg a0 = args[0];
+    TCGArg a1 = args[1];
 
     switch (opc) {
     case INDEX_op_mb:
@@ -401,6 +432,41 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
         break;
 
+    case INDEX_op_ext8s_i32:
+    case INDEX_op_ext8s_i64:
+        tcg_out_ext8s(s, a0, a1);
+        break;
+
+    case INDEX_op_ext8u_i32:
+    case INDEX_op_ext8u_i64:
+        tcg_out_ext8u(s, a0, a1);
+        break;
+
+    case INDEX_op_ext16s_i32:
+    case INDEX_op_ext16s_i64:
+        tcg_out_ext16s(s, a0, a1);
+        break;
+
+    case INDEX_op_ext16u_i32:
+    case INDEX_op_ext16u_i64:
+        tcg_out_ext16u(s, a0, a1);
+        break;
+
+    case INDEX_op_ext32u_i64:
+    case INDEX_op_extu_i32_i64:
+        tcg_out_ext32u(s, a0, a1);
+        break;
+
+    case INDEX_op_ext32s_i64:
+    case INDEX_op_extrl_i64_i32:
+    case INDEX_op_ext_i32_i64:
+        tcg_out_ext32s(s, a0, a1);
+        break;
+
+    case INDEX_op_extrh_i64_i32:
+        tcg_out_opc_srai_d(s, a0, a1, 32);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     default:
@@ -414,6 +480,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_goto_ptr:
         return C_O0_I1(r);
 
+    case INDEX_op_ext8s_i32:
+    case INDEX_op_ext8s_i64:
+    case INDEX_op_ext8u_i32:
+    case INDEX_op_ext8u_i64:
+    case INDEX_op_ext16s_i32:
+    case INDEX_op_ext16s_i64:
+    case INDEX_op_ext16u_i32:
+    case INDEX_op_ext16u_i64:
+    case INDEX_op_ext32s_i64:
+    case INDEX_op_ext32u_i64:
+    case INDEX_op_extu_i32_i64:
+    case INDEX_op_extrl_i64_i32:
+    case INDEX_op_extrh_i64_i32:
+    case INDEX_op_ext_i32_i64:
+        return C_O1_I1(r, r);
+
     default:
         g_assert_not_reached();
     }
-- 
2.25.1



  parent reply	other threads:[~2021-12-21 17:06 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-21 16:47 [PULL 00/31] tcg/loongarch64: New tcg backend Richard Henderson
2021-12-21 16:47 ` [PULL 01/31] elf: Add machine type value for LoongArch Richard Henderson
2021-12-21 16:47 ` [PULL 02/31] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer Richard Henderson
2021-12-21 16:47 ` [PULL 03/31] tcg/loongarch64: Add the tcg-target.h file Richard Henderson
2021-12-21 16:47 ` [PULL 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers Richard Henderson
2021-12-21 16:47 ` [PULL 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets Richard Henderson
2021-12-21 16:47 ` [PULL 06/31] tcg/loongarch64: Define the operand constraints Richard Henderson
2021-12-21 16:47 ` [PULL 07/31] tcg/loongarch64: Implement necessary relocation operations Richard Henderson
2021-12-21 16:47 ` [PULL 08/31] tcg/loongarch64: Implement the memory barrier op Richard Henderson
2021-12-21 16:47 ` [PULL 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi Richard Henderson
2021-12-21 16:47 ` [PULL 10/31] tcg/loongarch64: Implement goto_ptr Richard Henderson
2021-12-21 16:47 ` Richard Henderson [this message]
2021-12-21 16:47 ` [PULL 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops Richard Henderson
2021-12-21 16:47 ` [PULL 13/31] tcg/loongarch64: Implement deposit/extract ops Richard Henderson
2021-12-21 16:47 ` [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops Richard Henderson
2021-12-21 16:47 ` [PULL 15/31] tcg/loongarch64: Implement clz/ctz ops Richard Henderson
2021-12-21 16:47 ` [PULL 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops Richard Henderson
2021-12-21 16:47 ` [PULL 17/31] tcg/loongarch64: Implement add/sub ops Richard Henderson
2021-12-21 16:47 ` [PULL 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops Richard Henderson
2021-12-21 16:47 ` [PULL 19/31] tcg/loongarch64: Implement br/brcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 20/31] tcg/loongarch64: Implement setcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 21/31] tcg/loongarch64: Implement tcg_out_call Richard Henderson
2021-12-21 16:47 ` [PULL 22/31] tcg/loongarch64: Implement simple load/store ops Richard Henderson
2021-12-21 16:47 ` [PULL 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops Richard Henderson
2021-12-21 16:47 ` [PULL 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue Richard Henderson
2021-12-21 16:47 ` [PULL 25/31] tcg/loongarch64: Implement exit_tb/goto_tb Richard Henderson
2021-12-21 16:47 ` [PULL 26/31] tcg/loongarch64: Implement tcg_target_init Richard Henderson
2021-12-21 16:47 ` [PULL 27/31] tcg/loongarch64: Register the JIT Richard Henderson
2021-12-21 16:47 ` [PULL 28/31] common-user: Add safe syscall handling for loongarch64 hosts Richard Henderson
2021-12-21 16:47 ` [PULL 29/31] linux-user: Implement CPU-specific signal handler " Richard Henderson
2021-12-21 16:47 ` [PULL 30/31] configure, meson.build: Mark support " Richard Henderson
2021-12-21 16:47 ` [PULL 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab Richard Henderson

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