From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
Date: Tue, 21 Dec 2021 08:47:18 -0800 [thread overview]
Message-ID: <20211221164737.1076007-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211221164737.1076007-1-richard.henderson@linaro.org>
From: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-13-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 2 +
tcg/loongarch64/tcg-target.h | 16 ++---
tcg/loongarch64/tcg-target.c.inc | 88 ++++++++++++++++++++++++++++
3 files changed, 98 insertions(+), 8 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 7e459490ea..9ac24b8ad0 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -16,3 +16,5 @@
*/
C_O0_I1(r)
C_O1_I1(r, r)
+C_O1_I2(r, r, rC)
+C_O1_I2(r, r, rU)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index a6d9e036fc..cc9aecc681 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -113,13 +113,13 @@ typedef enum {
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0
-#define TCG_TARGET_HAS_not_i32 0
+#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 0
-#define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_orc_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
+#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_nor_i32 0
+#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 0
@@ -149,13 +149,13 @@ typedef enum {
#define TCG_TARGET_HAS_bswap16_i64 0
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
-#define TCG_TARGET_HAS_not_i64 0
+#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 0
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
+#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 25b58c7828..d9508d5295 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -422,6 +422,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
{
TCGArg a0 = args[0];
TCGArg a1 = args[1];
+ TCGArg a2 = args[2];
+ int c2 = const_args[2];
switch (opc) {
case INDEX_op_mb:
@@ -467,6 +469,68 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_srai_d(s, a0, a1, 32);
break;
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
+ break;
+
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ if (c2) {
+ tcg_out_opc_ori(s, a0, a1, a2);
+ tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
+ } else {
+ tcg_out_opc_nor(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ if (c2) {
+ /* guaranteed to fit due to constraint */
+ tcg_out_opc_andi(s, a0, a1, ~a2);
+ } else {
+ tcg_out_opc_andn(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ if (c2) {
+ /* guaranteed to fit due to constraint */
+ tcg_out_opc_ori(s, a0, a1, ~a2);
+ } else {
+ tcg_out_opc_orn(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ if (c2) {
+ tcg_out_opc_andi(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_and(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ if (c2) {
+ tcg_out_opc_ori(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_or(s, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ if (c2) {
+ tcg_out_opc_xori(s, a0, a1, a2);
+ } else {
+ tcg_out_opc_xor(s, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -494,8 +558,32 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
return C_O1_I1(r, r);
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ /*
+ * LoongArch insns for these ops don't have reg-imm forms, but we
+ * can express using andi/ori if ~constant satisfies
+ * TCG_CT_CONST_U12.
+ */
+ return C_O1_I2(r, r, rC);
+
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ /* LoongArch reg-imm bitops have their imms ZERO-extended */
+ return C_O1_I2(r, r, rU);
+
default:
g_assert_not_reached();
}
--
2.25.1
next prev parent reply other threads:[~2021-12-21 17:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 16:47 [PULL 00/31] tcg/loongarch64: New tcg backend Richard Henderson
2021-12-21 16:47 ` [PULL 01/31] elf: Add machine type value for LoongArch Richard Henderson
2021-12-21 16:47 ` [PULL 02/31] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer Richard Henderson
2021-12-21 16:47 ` [PULL 03/31] tcg/loongarch64: Add the tcg-target.h file Richard Henderson
2021-12-21 16:47 ` [PULL 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers Richard Henderson
2021-12-21 16:47 ` [PULL 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets Richard Henderson
2021-12-21 16:47 ` [PULL 06/31] tcg/loongarch64: Define the operand constraints Richard Henderson
2021-12-21 16:47 ` [PULL 07/31] tcg/loongarch64: Implement necessary relocation operations Richard Henderson
2021-12-21 16:47 ` [PULL 08/31] tcg/loongarch64: Implement the memory barrier op Richard Henderson
2021-12-21 16:47 ` [PULL 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi Richard Henderson
2021-12-21 16:47 ` [PULL 10/31] tcg/loongarch64: Implement goto_ptr Richard Henderson
2021-12-21 16:47 ` [PULL 11/31] tcg/loongarch64: Implement sign-/zero-extension ops Richard Henderson
2021-12-21 16:47 ` Richard Henderson [this message]
2021-12-21 16:47 ` [PULL 13/31] tcg/loongarch64: Implement deposit/extract ops Richard Henderson
2021-12-21 16:47 ` [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops Richard Henderson
2021-12-21 16:47 ` [PULL 15/31] tcg/loongarch64: Implement clz/ctz ops Richard Henderson
2021-12-21 16:47 ` [PULL 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops Richard Henderson
2021-12-21 16:47 ` [PULL 17/31] tcg/loongarch64: Implement add/sub ops Richard Henderson
2021-12-21 16:47 ` [PULL 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops Richard Henderson
2021-12-21 16:47 ` [PULL 19/31] tcg/loongarch64: Implement br/brcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 20/31] tcg/loongarch64: Implement setcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 21/31] tcg/loongarch64: Implement tcg_out_call Richard Henderson
2021-12-21 16:47 ` [PULL 22/31] tcg/loongarch64: Implement simple load/store ops Richard Henderson
2021-12-21 16:47 ` [PULL 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops Richard Henderson
2021-12-21 16:47 ` [PULL 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue Richard Henderson
2021-12-21 16:47 ` [PULL 25/31] tcg/loongarch64: Implement exit_tb/goto_tb Richard Henderson
2021-12-21 16:47 ` [PULL 26/31] tcg/loongarch64: Implement tcg_target_init Richard Henderson
2021-12-21 16:47 ` [PULL 27/31] tcg/loongarch64: Register the JIT Richard Henderson
2021-12-21 16:47 ` [PULL 28/31] common-user: Add safe syscall handling for loongarch64 hosts Richard Henderson
2021-12-21 16:47 ` [PULL 29/31] linux-user: Implement CPU-specific signal handler " Richard Henderson
2021-12-21 16:47 ` [PULL 30/31] configure, meson.build: Mark support " Richard Henderson
2021-12-21 16:47 ` [PULL 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab Richard Henderson
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