From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 18/31] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
Date: Tue, 21 Dec 2021 08:47:24 -0800 [thread overview]
Message-ID: <20211221164737.1076007-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211221164737.1076007-1-richard.henderson@linaro.org>
From: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-19-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.h | 16 +++----
tcg/loongarch64/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++
3 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 4b8ce85897..fb56f3a295 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -23,3 +23,4 @@ C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index d1ded50cb0..05010805e7 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -93,8 +93,8 @@ typedef enum {
/* optional instructions */
#define TCG_TARGET_HAS_movcond_i32 0
-#define TCG_TARGET_HAS_div_i32 0
-#define TCG_TARGET_HAS_rem_i32 0
+#define TCG_TARGET_HAS_div_i32 1
+#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
@@ -105,8 +105,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
-#define TCG_TARGET_HAS_muluh_i32 0
-#define TCG_TARGET_HAS_mulsh_i32 0
+#define TCG_TARGET_HAS_muluh_i32 1
+#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
@@ -130,8 +130,8 @@ typedef enum {
/* 64-bit operations */
#define TCG_TARGET_HAS_movcond_i64 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
@@ -163,8 +163,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
/* not defined -- call should be eliminated at compile time */
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index c71d25d3fe..0ae193fba5 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -717,6 +717,55 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_mul_i32:
+ tcg_out_opc_mul_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mul_i64:
+ tcg_out_opc_mul_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_mulsh_i32:
+ tcg_out_opc_mulh_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_opc_mulh_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_muluh_i32:
+ tcg_out_opc_mulh_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_muluh_i64:
+ tcg_out_opc_mulh_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out_opc_div_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_div_i64:
+ tcg_out_opc_div_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_divu_i32:
+ tcg_out_opc_div_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ tcg_out_opc_div_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i32:
+ tcg_out_opc_mod_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_rem_i64:
+ tcg_out_opc_mod_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_remu_i32:
+ tcg_out_opc_mod_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_remu_i64:
+ tcg_out_opc_mod_du(s, a0, a1, a2);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -808,6 +857,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub_i64:
return C_O1_I2(r, rZ, rN);
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ return C_O1_I2(r, rZ, rZ);
+
default:
g_assert_not_reached();
}
--
2.25.1
next prev parent reply other threads:[~2021-12-21 17:00 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-21 16:47 [PULL 00/31] tcg/loongarch64: New tcg backend Richard Henderson
2021-12-21 16:47 ` [PULL 01/31] elf: Add machine type value for LoongArch Richard Henderson
2021-12-21 16:47 ` [PULL 02/31] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer Richard Henderson
2021-12-21 16:47 ` [PULL 03/31] tcg/loongarch64: Add the tcg-target.h file Richard Henderson
2021-12-21 16:47 ` [PULL 04/31] tcg/loongarch64: Add generated instruction opcodes and encoding helpers Richard Henderson
2021-12-21 16:47 ` [PULL 05/31] tcg/loongarch64: Add register names, allocation order and input/output sets Richard Henderson
2021-12-21 16:47 ` [PULL 06/31] tcg/loongarch64: Define the operand constraints Richard Henderson
2021-12-21 16:47 ` [PULL 07/31] tcg/loongarch64: Implement necessary relocation operations Richard Henderson
2021-12-21 16:47 ` [PULL 08/31] tcg/loongarch64: Implement the memory barrier op Richard Henderson
2021-12-21 16:47 ` [PULL 09/31] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi Richard Henderson
2021-12-21 16:47 ` [PULL 10/31] tcg/loongarch64: Implement goto_ptr Richard Henderson
2021-12-21 16:47 ` [PULL 11/31] tcg/loongarch64: Implement sign-/zero-extension ops Richard Henderson
2021-12-21 16:47 ` [PULL 12/31] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops Richard Henderson
2021-12-21 16:47 ` [PULL 13/31] tcg/loongarch64: Implement deposit/extract ops Richard Henderson
2021-12-21 16:47 ` [PULL 14/31] tcg/loongarch64: Implement bswap{16,32,64} ops Richard Henderson
2021-12-21 16:47 ` [PULL 15/31] tcg/loongarch64: Implement clz/ctz ops Richard Henderson
2021-12-21 16:47 ` [PULL 16/31] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops Richard Henderson
2021-12-21 16:47 ` [PULL 17/31] tcg/loongarch64: Implement add/sub ops Richard Henderson
2021-12-21 16:47 ` Richard Henderson [this message]
2021-12-21 16:47 ` [PULL 19/31] tcg/loongarch64: Implement br/brcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 20/31] tcg/loongarch64: Implement setcond ops Richard Henderson
2021-12-21 16:47 ` [PULL 21/31] tcg/loongarch64: Implement tcg_out_call Richard Henderson
2021-12-21 16:47 ` [PULL 22/31] tcg/loongarch64: Implement simple load/store ops Richard Henderson
2021-12-21 16:47 ` [PULL 23/31] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops Richard Henderson
2021-12-21 16:47 ` [PULL 24/31] tcg/loongarch64: Implement tcg_target_qemu_prologue Richard Henderson
2021-12-21 16:47 ` [PULL 25/31] tcg/loongarch64: Implement exit_tb/goto_tb Richard Henderson
2021-12-21 16:47 ` [PULL 26/31] tcg/loongarch64: Implement tcg_target_init Richard Henderson
2021-12-21 16:47 ` [PULL 27/31] tcg/loongarch64: Register the JIT Richard Henderson
2021-12-21 16:47 ` [PULL 28/31] common-user: Add safe syscall handling for loongarch64 hosts Richard Henderson
2021-12-21 16:47 ` [PULL 29/31] linux-user: Implement CPU-specific signal handler " Richard Henderson
2021-12-21 16:47 ` [PULL 30/31] configure, meson.build: Mark support " Richard Henderson
2021-12-21 16:47 ` [PULL 31/31] tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211221164737.1076007-19-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=f4bug@amsat.org \
--cc=git@xen0n.name \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).