[PATCH 3/8] target/ppc/power8-pmu-insn-cnt: add pmu_inc_pmc1()

[Daniel Henrique Barboza <danielhb413@gmail.com>]

pmu_inc_pmc1() will use TCG Ops to increment the PMC1 counter when
it's counting PM_INST_CMPL events. At this moment we're supporting two
values of MMCR1_PMC1SEL for this event: 0x02 and 0xFE.

This function, and all the soon to be added PMC2-4 insn count functions,
does not check if MMCR0_FC14 is set. This check is done inside
pmu_count_insns, which will allow us to skip all PMC1-4 instruction
count functions at once if the proper conditions aren't met.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 target/ppc/power8-pmu-insn-cnt.c.inc | 76 ++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/target/ppc/power8-pmu-insn-cnt.c.inc b/target/ppc/power8-pmu-insn-cnt.c.inc
index c683573104..3661fb0022 100644
--- a/target/ppc/power8-pmu-insn-cnt.c.inc
+++ b/target/ppc/power8-pmu-insn-cnt.c.inc
@@ -11,6 +11,56 @@
  */
 
 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+#define MMCR1_PMC1_INS_CNT        0x02000000
+#define MMCR1_PMC1_INS_CNT2       0xFE000000
+
+/*
+ * Increments PMC1 checking if MMCR1_PMC1SEL has one of the following
+ * events:
+ *
+ * - 0x02: implementation dependent PM_INSN_CMPL
+ * - 0xFE: ISA architected PM_INSN_CMPL
+ *
+ * This function assumes that MMCR0_FC14 is cleared.
+ */
+static void pmu_inc_pmc1(DisasContext *ctx)
+{
+    TCGv t0, t1, t2;
+    TCGLabel *l_inc_pmc;
+    TCGLabel *l_skip_pmc;
+
+    /*
+     * PMC1 will be incremented if MMCR1_PMC1SEL = 0x2
+     * or 0xFE.
+     */
+    l_inc_pmc = gen_new_label();
+    l_skip_pmc = gen_new_label();
+
+    t0 = tcg_temp_new();
+    gen_load_spr(t0, SPR_POWER_MMCR1);
+    tcg_gen_andi_tl(t0, t0, MMCR1_PMC1_INS_CNT);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, MMCR1_PMC1_INS_CNT, l_inc_pmc);
+
+    t1 = tcg_temp_new();
+    gen_load_spr(t1, SPR_POWER_MMCR1);
+    tcg_gen_andi_tl(t1, t1, MMCR1_PMC1_INS_CNT2);
+    tcg_gen_brcondi_tl(TCG_COND_NE, t1, MMCR1_PMC1_INS_CNT2, l_skip_pmc);
+
+    gen_set_label(l_inc_pmc);
+
+    t2 = tcg_temp_new();
+    gen_load_spr(t2, SPR_POWER_PMC1);
+    tcg_gen_addi_tl(t2, t2, ctx->base.num_insns);
+    gen_store_spr(SPR_POWER_PMC1, t2);
+
+    gen_set_label(l_skip_pmc);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
+}
+
 /*
  * Increments PMC5 if MMCR0_FC is cleared.
  */
@@ -55,8 +105,34 @@ static void pmu_count_insns(DisasContext *ctx)
 
  #if !defined(CONFIG_USER_ONLY)
 
+    TCGv t_mmcr0, t_mmcr1;
+    TCGLabel *l_skip_pmc14;
+
     pmu_inc_pmc5(ctx);
 
+    /*
+     * Skip PMC1-4 increment if:
+     * - MMCR0_FC14 is set OR
+     * - MMCR1 is cleared
+     */
+    l_skip_pmc14 = gen_new_label();
+
+    t_mmcr0 = tcg_temp_new();
+    gen_load_spr(t_mmcr0, SPR_POWER_MMCR0);
+    tcg_gen_andi_tl(t_mmcr0, t_mmcr0, MMCR0_FC14);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr0, MMCR0_FC14, l_skip_pmc14);
+
+    t_mmcr1 = tcg_temp_new();
+    gen_load_spr(t_mmcr1, SPR_POWER_MMCR1);
+    tcg_gen_brcondi_tl(TCG_COND_EQ, t_mmcr1, 0x0, l_skip_pmc14);
+
+    pmu_inc_pmc1(ctx);
+
+    gen_set_label(l_skip_pmc14);
+
+    tcg_temp_free(t_mmcr0);
+    tcg_temp_free(t_mmcr1);
+
 #else
     /*
      * User mode can read (but not write) PMC5 and start/stop
-- 
2.33.1