From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, danielhb413@gmail.com,
qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au
Subject: [PATCH v2 1/5] target/ppc: powerpc_excp: Set alternate SRRs directly
Date: Wed, 29 Dec 2021 13:57:47 -0300 [thread overview]
Message-ID: <20211229165751.3774248-2-farosas@linux.ibm.com> (raw)
In-Reply-To: <20211229165751.3774248-1-farosas@linux.ibm.com>
There are currently only two interrupts that use alternate SRRs, so
let them write to them directly during the setup code.
No functional change intended.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/excp_helper.c | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f90e616aac..8b9c6bc5a8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -298,7 +298,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1, asrr0, asrr1, lev = -1;
+ int srr0, srr1, lev = -1;
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code);
@@ -319,8 +319,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* target registers */
srr0 = SPR_SRR0;
srr1 = SPR_SRR1;
- asrr0 = -1;
- asrr1 = -1;
/*
* check for special resume at 0x100 from doze/nap/sleep/winkle on
@@ -410,8 +408,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_MCSRR0;
srr1 = SPR_BOOKE_MCSRR1;
- asrr0 = SPR_BOOKE_CSRR0;
- asrr1 = SPR_BOOKE_CSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
break;
default:
break;
@@ -570,8 +569,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* FIXME: choose one or the other based on CPU type */
srr0 = SPR_BOOKE_DSRR0;
srr1 = SPR_BOOKE_DSRR1;
- asrr0 = SPR_BOOKE_CSRR0;
- asrr1 = SPR_BOOKE_CSRR1;
+
+ env->spr[SPR_BOOKE_CSRR0] = env->nip;
+ env->spr[SPR_BOOKE_CSRR1] = msr;
+
/* DBSR already modified by caller */
} else {
cpu_abort(cs, "Debug exception triggered on unsupported model\n");
@@ -838,14 +839,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
vector |= env->excp_prefix;
- /* If any alternate SRR register are defined, duplicate saved values */
- if (asrr0 != -1) {
- env->spr[asrr0] = env->nip;
- }
- if (asrr1 != -1) {
- env->spr[asrr1] = msr;
- }
-
#if defined(TARGET_PPC64)
if (excp_model == POWERPC_EXCP_BOOKE) {
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
--
2.33.1
next prev parent reply other threads:[~2021-12-29 17:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-29 16:57 [PATCH v2 0/5] target/ppc: powerpc_excp improvements (1/n) Fabiano Rosas
2021-12-29 16:57 ` Fabiano Rosas [this message]
2021-12-29 16:57 ` [PATCH v2 2/5] target/ppc: powerpc_excp: Add excp_vectors bounds check Fabiano Rosas
2021-12-30 22:04 ` Richard Henderson
2021-12-31 7:40 ` Cédric Le Goater
2022-01-01 8:29 ` David Gibson
2021-12-29 16:57 ` [PATCH v2 3/5] target/ppc: powerpc_excp: Set vector earlier Fabiano Rosas
2021-12-30 22:05 ` Richard Henderson
2022-01-01 8:31 ` David Gibson
2021-12-29 16:57 ` [PATCH v2 4/5] target/ppc: powerpc_excp: Move system call vectored code together Fabiano Rosas
2021-12-29 16:57 ` [PATCH v2 5/5] target/ppc: powerpc_excp: Stop passing excp_model around Fabiano Rosas
2022-01-04 7:40 ` [PATCH v2 0/5] target/ppc: powerpc_excp improvements (1/n) Cédric Le Goater
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