From: liweiwei <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, liweiwei <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com
Subject: [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
Date: Thu, 30 Dec 2021 22:30:52 +0800 [thread overview]
Message-ID: <20211230143058.7352-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20211230143058.7352-1-liweiwei@iscas.ac.cn>
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 13 +++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bce..961c5f4334 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -491,6 +491,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_d = true;
}
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zkr = true;
+ cpu->cfg.ext_zkt = true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zknh = true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dc10f27093..edca7118ff 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -311,7 +311,20 @@ struct RISCVCPU {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.17.1
next prev parent reply other threads:[~2021-12-30 14:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-30 14:30 [PATCH v3 0/7] support subsets of scalar crypto extension liweiwei
2021-12-30 14:30 ` liweiwei [this message]
2021-12-31 2:04 ` [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk* Bin Meng
2021-12-31 2:29 ` liweiwei
2021-12-30 14:30 ` [PATCH v3 2/7] target/riscv: rvk: add implementation of instructions for Zbk* liweiwei
2021-12-30 14:30 ` [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto liweiwei
2021-12-30 14:46 ` Philippe Mathieu-Daudé
2021-12-30 15:24 ` liweiwei
2021-12-30 14:30 ` [PATCH v3 4/7] target/riscv: rvk: add implementation of instructions for Zk* liweiwei
2021-12-30 14:30 ` [PATCH v3 5/7] target/riscv: rvk: add CSR support for Zkr liweiwei
2021-12-30 14:30 ` [PATCH v3 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions liweiwei
2021-12-30 14:30 ` [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties liweiwei
2022-01-10 7:06 ` Alistair Francis
2022-01-10 7:44 ` Weiwei Li
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