From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, liweiwei <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, ardxwe@gmail.com
Subject: [PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
Date: Fri, 31 Dec 2021 11:23:37 +0800 [thread overview]
Message-ID: <20211231032337.15579-7-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20211231032337.15579-1-liweiwei@iscas.ac.cn>
From: liweiwei <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc7da446f1..3dd07759e1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -661,6 +661,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
--
2.17.1
prev parent reply other threads:[~2021-12-31 3:30 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-31 3:23 [PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li
2021-12-31 3:23 ` [PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li
2021-12-31 6:28 ` Bin Meng
2021-12-31 3:23 ` [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li
2021-12-31 19:56 ` Richard Henderson
2022-01-01 5:55 ` Weiwei Li
2022-01-01 19:46 ` Richard Henderson
2022-01-02 5:53 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 3/6] target/riscv: add support for zfinx Weiwei Li
2021-12-31 20:03 ` Richard Henderson
2021-12-31 20:06 ` Richard Henderson
2022-01-01 6:05 ` Weiwei Li
2022-01-01 19:48 ` Richard Henderson
2022-01-02 5:56 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 4/6] target/riscv: add support for zdinx Weiwei Li
2021-12-31 20:07 ` Richard Henderson
2022-01-01 6:06 ` Weiwei Li
2021-12-31 3:23 ` [PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li
2021-12-31 20:08 ` Richard Henderson
2021-12-31 3:23 ` Weiwei Li [this message]
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