From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: git@xen0n.name, peter.maydell@linaro.org
Subject: [PATCH v4 7/7] tests/tcg/multiarch: Add sigbus.c
Date: Mon, 3 Jan 2022 18:15:43 -0800 [thread overview]
Message-ID: <20220104021543.396571-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220104021543.396571-1-richard.henderson@linaro.org>
A mostly generic test for unaligned access raising SIGBUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 tests/tcg/multiarch/sigbus.c
diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c
new file mode 100644
index 0000000000..8134c5fd56
--- /dev/null
+++ b/tests/tcg/multiarch/sigbus.c
@@ -0,0 +1,68 @@
+#define _GNU_SOURCE 1
+
+#include <assert.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <endian.h>
+
+
+unsigned long long x = 0x8877665544332211ull;
+void * volatile p = (void *)&x + 1;
+
+void sigbus(int sig, siginfo_t *info, void *uc)
+{
+ assert(sig == SIGBUS);
+ assert(info->si_signo == SIGBUS);
+#ifdef BUS_ADRALN
+ assert(info->si_code == BUS_ADRALN);
+#endif
+ assert(info->si_addr == p);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ struct sigaction sa = {
+ .sa_sigaction = sigbus,
+ .sa_flags = SA_SIGINFO
+ };
+ int allow_fail = 0;
+ int tmp;
+
+ tmp = sigaction(SIGBUS, &sa, NULL);
+ assert(tmp == 0);
+
+ /*
+ * Select an operation that's likely to enforce alignment.
+ * On many guests that support unaligned accesses by default,
+ * this is often an atomic operation.
+ */
+#if defined(__aarch64__)
+ asm volatile("ldxr %w0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__alpha__)
+ asm volatile("ldl_l %0,0(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__arm__)
+ asm volatile("ldrex %0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__powerpc__)
+ asm volatile("lwarx %0,0,%1" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__riscv_atomic)
+ asm volatile("lr.w %0,(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#else
+ /* No insn known to fault unaligned -- try for a straight load. */
+ allow_fail = 1;
+ tmp = *(volatile int *)p;
+#endif
+
+ assert(allow_fail);
+
+ /*
+ * We didn't see a signal.
+ * We might as well validate the unaligned load worked.
+ */
+ if (BYTE_ORDER == LITTLE_ENDIAN) {
+ assert(tmp == 0x55443322);
+ } else {
+ assert(tmp == 0x77665544);
+ }
+ return EXIT_SUCCESS;
+}
--
2.25.1
next prev parent reply other threads:[~2022-01-04 2:23 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 2:15 [PATCH v4 0/7] Unaligned access for user only Richard Henderson
2022-01-04 2:15 ` [PATCH v4 1/7] tcg/i386: Support raising sigbus for user-only Richard Henderson
2022-01-04 2:15 ` [PATCH v4 2/7] tcg/aarch64: " Richard Henderson
2022-01-06 14:41 ` Peter Maydell
2022-01-04 2:15 ` [PATCH v4 3/7] tcg/ppc: " Richard Henderson
2022-01-04 2:15 ` [PATCH v4 4/7] tcg/riscv: " Richard Henderson
2022-01-04 2:15 ` [PATCH v4 5/7] tcg/s390x: " Richard Henderson
2022-01-04 2:15 ` [PATCH v4 6/7] tcg/tci: " Richard Henderson
2022-01-04 14:01 ` Philippe Mathieu-Daudé
2022-01-04 2:15 ` Richard Henderson [this message]
2022-01-04 14:06 ` [PATCH v4 7/7] tests/tcg/multiarch: Add sigbus.c Philippe Mathieu-Daudé
2022-01-07 12:04 ` Alex Bennée
2022-01-04 3:13 ` [PATCH v4 0/7] Unaligned access for user only WANG Xuerui
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