From: Jim Shu <jim.shu@sifive.com>
To: Alistair.Francis@wdc.com, bin.meng@windriver.com,
palmer@dabbelt.com, frank.chang@sifive.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Jim Shu <jim.shu@sifive.com>
Subject: [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
Date: Tue, 4 Jan 2022 14:34:06 +0800 [thread overview]
Message-ID: <20220104063408.658169-1-jim.shu@sifive.com> (raw)
HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation supports low part access now. Enhance QEMU
emulation to support high 32-bit access.
Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.
Changelog:
v2:
* Fix high 32-bit write access of 64-bit RO registers
* Fix commit log
Jim Shu (2):
hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
hw/dma/sifive_pdma.c | 181 +++++++++++++++++++++++++++++++++++++------
1 file changed, 159 insertions(+), 22 deletions(-)
--
2.25.1
next reply other threads:[~2022-01-04 6:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 6:34 Jim Shu [this message]
2022-01-04 6:34 ` [PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Jim Shu
2022-01-04 6:34 ` [PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Jim Shu
2022-01-04 21:54 ` [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware Alistair Francis
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