qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Jim Shu <jim.shu@sifive.com>
To: Alistair.Francis@wdc.com, bin.meng@windriver.com,
	palmer@dabbelt.com, frank.chang@sifive.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Jim Shu" <jim.shu@sifive.com>
Subject: [PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
Date: Tue,  4 Jan 2022 14:34:08 +0800	[thread overview]
Message-ID: <20220104063408.658169-3-jim.shu@sifive.com> (raw)
In-Reply-To: <20220104063408.658169-1-jim.shu@sifive.com>

It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 hw/dma/sifive_pdma.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index f4df16449b..1dd88f3479 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -444,6 +444,10 @@ static const MemoryRegionOps sifive_pdma_ops = {
     .impl = {
         .min_access_size = 4,
         .max_access_size = 8,
+    },
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 8,
     }
 };
 
-- 
2.25.1



  parent reply	other threads:[~2022-01-04  6:45 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-04  6:34 [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware Jim Shu
2022-01-04  6:34 ` [PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Jim Shu
2022-01-04  6:34 ` Jim Shu [this message]
2022-01-04 21:54 ` [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220104063408.658169-3-jim.shu@sifive.com \
    --to=jim.shu@sifive.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=bmeng.cn@gmail.com \
    --cc=frank.chang@sifive.com \
    --cc=palmer@dabbelt.com \
    --cc=philmd@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).