From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: "Christophe Leroy" <christophe.leroy@c-s.fr>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 12/26] ppc/ppc405: Restore TCR and STR write handlers
Date: Tue, 4 Jan 2022 08:31:07 +0100 [thread overview]
Message-ID: <20220104073121.3784280-13-clg@kaod.org> (raw)
In-Reply-To: <20220104073121.3784280-1-clg@kaod.org>
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :
SPR_BOOKE_TSR (0x150)
SPR_BOOKE_TCR (0x154)
SPR_40x_TSR (0x3D8)
SPR_40x_TCR (0x3DA)
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Fixes: ddd1055b07fd ("PPC: booke timers")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/spr_tcg.h | 2 ++
hw/ppc/ppc.c | 25 +++++++++++++++++++++++++
target/ppc/cpu_init.c | 4 ++--
target/ppc/timebase_helper.c | 10 ++++++++++
target/ppc/translate.c | 12 ++++++++++++
hw/ppc/trace-events | 2 ++
8 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fc66c3561dab..4808e10ebe8b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1399,6 +1399,8 @@ target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
void store_40x_sler(CPUPPCState *env, uint32_t val);
+void store_40x_tcr(CPUPPCState *env, target_ulong val);
+void store_40x_tsr(CPUPPCState *env, target_ulong val);
void store_booke_tcr(CPUPPCState *env, target_ulong val);
void store_booke_tsr(CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all(CPUPPCState *env);
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fb6cac38b4c5..f9c72dcd504d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -706,6 +706,8 @@ DEF_HELPER_2(store_hid0_601, void, env, tl)
DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(store_40x_tsr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_40x_dbcr0, void, env, tl)
DEF_HELPER_2(store_40x_sler, void, env, tl)
DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index f98d97c0ba17..64cf5302cb86 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -87,6 +87,8 @@ void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn);
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn);
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn);
+void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn);
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn);
void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 818d75798584..cca99cb86f81 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1300,6 +1300,31 @@ target_ulong load_40x_pit (CPUPPCState *env)
return cpu_ppc_load_decr(env);
}
+void store_40x_tsr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+
+ trace_ppc40x_store_tcr(val);
+
+ env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
+ if (val & 0x80000000) {
+ ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
+ }
+}
+
+void store_40x_tcr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ ppc_tb_t *tb_env;
+
+ trace_ppc40x_store_tsr(val);
+
+ tb_env = env->tb_env;
+ env->spr[SPR_40x_TCR] = val & 0xFFC00000;
+ start_stop_pit(env, tb_env, 1);
+ cpu_4xx_wdt_cb(cpu);
+}
+
static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
{
CPUPPCState *env = opaque;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 06ef15cd9e4e..b5e2fde9ec4d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1440,11 +1440,11 @@ static void register_40x_sprs(CPUPPCState *env)
0x00000000);
spr_register(env, SPR_40x_TCR, "TCR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tcr,
+ &spr_read_generic, &spr_write_40x_tcr,
0x00000000);
spr_register(env, SPR_40x_TSR, "TSR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_booke_tsr,
+ &spr_read_generic, &spr_write_40x_tsr,
0x00000000);
}
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 8ff4080eb91e..af378318c19c 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -144,6 +144,16 @@ void helper_store_40x_pit(CPUPPCState *env, target_ulong val)
store_40x_pit(env, val);
}
+void helper_store_40x_tcr(CPUPPCState *env, target_ulong val)
+{
+ store_40x_tcr(env, val);
+}
+
+void helper_store_40x_tsr(CPUPPCState *env, target_ulong val)
+{
+ store_40x_tsr(env, val);
+}
+
void helper_store_booke_tcr(CPUPPCState *env, target_ulong val)
{
store_booke_tcr(env, val);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 114456148c4b..eb45f679d34f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -878,6 +878,18 @@ void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
}
+void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_icount_io_start(ctx);
+ gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
+}
+
+void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_icount_io_start(ctx);
+ gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
+}
+
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 0c55aa501471..5c0a215cad90 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -110,6 +110,8 @@ ppc4xx_pit_start(uint64_t reload) "PIT 0x%016" PRIx64
ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64 " PIT 0x%016" PRIx64
ppc4xx_wdt(uint64_t tcr, uint64_t tsr) "TCR 0x%" PRIx64 " TSR 0x%" PRIx64
ppc40x_store_pit(uint64_t value) "val 0x%" PRIx64
+ppc40x_store_tcr(uint64_t value) "val 0x%" PRIx64
+ppc40x_store_tsr(uint64_t value) "val 0x%" PRIx64
ppc40x_set_tb_clk(uint32_t value) "new frequency %" PRIu32
ppc40x_timers_init(uint32_t value) "frequency %" PRIu32
--
2.31.1
next prev parent reply other threads:[~2022-01-04 7:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-04 7:30 [PULL 00/26] ppc queue Cédric Le Goater
2022-01-04 7:30 ` [PULL 01/26] ppc/pnv: Change the maximum of PHB3 devices for Power8NVL Cédric Le Goater
2022-01-04 7:30 ` [PULL 02/26] ppc/pnv: Remove PHB4 reset handler Cédric Le Goater
2022-01-04 7:30 ` [PULL 03/26] ppc/pnv: Remove the PHB4 "device-id" property Cédric Le Goater
2022-01-04 7:30 ` [PULL 04/26] pnv_phb3.c: do not set 'root-bus' as bus name Cédric Le Goater
2022-01-04 7:31 ` [PULL 05/26] pnv_phb4.c: " Cédric Le Goater
2022-01-04 7:31 ` [PULL 06/26] target/ppc: Improve logging in Radix MMU Cédric Le Goater
2022-01-11 16:51 ` Peter Maydell
2022-01-11 17:28 ` Cédric Le Goater
2022-01-04 7:31 ` [PULL 07/26] target/ppc: Check effective address validity Cédric Le Goater
2022-01-04 7:31 ` [PULL 08/26] target/ppc: Remove static inline Cédric Le Goater
2022-01-04 7:31 ` [PULL 09/26] target/ppc: Print out literal exception names in logs Cédric Le Goater
2022-01-04 7:31 ` [PULL 10/26] ppc/ppc4xx: Convert printfs() Cédric Le Goater
2022-01-04 7:31 ` [PULL 11/26] ppc/ppc405: Activate MMU logs Cédric Le Goater
2022-01-04 7:31 ` Cédric Le Goater [this message]
2022-01-04 7:31 ` [PULL 13/26] ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU Cédric Le Goater
2022-01-04 7:31 ` [PULL 14/26] ppc/ppc405: Fix timer initialization Cédric Le Goater
2022-01-04 7:31 ` [PULL 15/26] ppc/ppc405: Introduce a store helper for SPR_40x_PID Cédric Le Goater
2022-01-04 7:31 ` [PULL 16/26] ppc/ppc405: Dump specific registers Cédric Le Goater
2022-01-04 7:31 ` [PULL 17/26] target/ppc: do not silence snan in xscvspdpn Cédric Le Goater
2022-01-04 7:31 ` [PULL 18/26] target/ppc: powerpc_excp: Set alternate SRRs directly Cédric Le Goater
2022-01-04 7:31 ` [PULL 19/26] target/ppc: powerpc_excp: Add excp_vectors bounds check Cédric Le Goater
2022-01-04 7:31 ` [PULL 20/26] target/ppc: powerpc_excp: Set vector earlier Cédric Le Goater
2022-01-04 7:31 ` [PULL 21/26] target/ppc: powerpc_excp: Move system call vectored code together Cédric Le Goater
2022-01-04 7:31 ` [PULL 22/26] target/ppc: powerpc_excp: Stop passing excp_model around Cédric Le Goater
2022-01-04 7:31 ` [PULL 23/26] target/ppc: Cache per-pmc insn and cycle count settings Cédric Le Goater
2022-01-04 7:31 ` [PULL 24/26] target/ppc: Rewrite pmu_increment_insns Cédric Le Goater
2022-01-04 7:31 ` [PULL 25/26] target/ppc: Use env->pnc_cyc_cnt Cédric Le Goater
2022-01-04 7:31 ` [PULL 26/26] target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0() Cédric Le Goater
2022-01-04 17:55 ` [PULL 00/26] ppc queue Richard Henderson
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