[PATCH v4 0/8] A collection of RISC-V cleanups and improvements

[Alistair Francis <alistair.francis@opensource.wdc.com>]

From: Alistair Francis <alistair.francis@wdc.com>

This is a few patches to cleanup some RISC-V hardware and mark the
Hyperisor extension as non experimental.

v4:
 - Resend
v3:
 - Drop some patches
 - Few small fixes from reviews
v2:
 - Add some more fixes
 - Address review comments

Alistair Francis (8):
  hw/intc: sifive_plic: Add a reset function
  hw/intc: sifive_plic: Cleanup the write function
  hw/intc: sifive_plic: Cleanup the read function
  hw/intc: sifive_plic: Cleanup remaining functions
  target/riscv: Mark the Hypervisor extension as non experimental
  target/riscv: Enable the Hypervisor extension by default
  hw/riscv: Use error_fatal for SoC realisation
  hw/riscv: virt: Allow support for 32 cores

 include/hw/riscv/virt.h    |   2 +-
 hw/intc/sifive_plic.c      | 254 +++++++++++--------------------------
 hw/riscv/microchip_pfsoc.c |   2 +-
 hw/riscv/opentitan.c       |   2 +-
 hw/riscv/sifive_e.c        |   2 +-
 hw/riscv/sifive_u.c        |   2 +-
 target/riscv/cpu.c         |   2 +-
 7 files changed, 82 insertions(+), 184 deletions(-)

-- 
2.31.1