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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, "Palmer Dabbelt" <palmer@dabbelt.com>,
	alistair23@gmail.com,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v4 1/8] hw/intc: sifive_plic: Add a reset function
Date: Thu,  6 Jan 2022 07:39:30 +1000	[thread overview]
Message-ID: <20220105213937.1113508-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com>

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 hw/intc/sifive_plic.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..a9f7a1bfb0 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -355,6 +355,23 @@ static const MemoryRegionOps sifive_plic_ops = {
     }
 };
 
+static void sifive_plic_reset(DeviceState *dev)
+{
+    SiFivePLICState *s = SIFIVE_PLIC(dev);
+    int i;
+
+    memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
+    memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
+    memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
+    memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
+    memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
+
+    for (i = 0; i < s->num_harts; i++) {
+        qemu_set_irq(s->m_external_irqs[i], 0);
+        qemu_set_irq(s->s_external_irqs[i], 0);
+    }
+}
+
 /*
  * parse PLIC hart/mode address offset config
  *
@@ -501,6 +518,7 @@ static void sifive_plic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
+    dc->reset = sifive_plic_reset;
     device_class_set_props(dc, sifive_plic_properties);
     dc->realize = sifive_plic_realize;
     dc->vmsd = &vmstate_sifive_plic;
-- 
2.31.1



  reply	other threads:[~2022-01-05 22:11 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-05 21:39 [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis
2022-01-05 21:39 ` Alistair Francis [this message]
2022-01-05 21:39 ` [PATCH v4 2/8] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2022-01-05 21:39 ` [PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2022-01-05 21:39 ` [PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2022-01-05 21:39 ` [PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2022-01-05 21:39 ` [PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2022-01-05 22:28 ` [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis

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