From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, Palmer Dabbelt <palmer@dabbelt.com>,
alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Anup Patel <anup.patel@wdc.com>
Subject: [PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default
Date: Thu, 6 Jan 2022 07:39:35 +1000 [thread overview]
Message-ID: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9ea67bedd3..29749e834f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -627,7 +627,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
- DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
--
2.31.1
next prev parent reply other threads:[~2022-01-05 22:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-05 21:39 [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis
2022-01-05 21:39 ` [PATCH v4 1/8] hw/intc: sifive_plic: Add a reset function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 2/8] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2022-01-05 21:39 ` [PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2022-01-05 21:39 ` Alistair Francis [this message]
2022-01-05 21:39 ` [PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2022-01-05 21:39 ` [PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2022-01-05 22:28 ` [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis
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