From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: bmeng.cn@gmail.com, "Palmer Dabbelt" <palmer@dabbelt.com>,
alistair23@gmail.com,
"Alistair Francis" <alistair.francis@wdc.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Anup Patel" <anup.patel@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores
Date: Thu, 6 Jan 2022 07:39:37 +1000 [thread overview]
Message-ID: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220105213937.1113508-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b8ef99f348..6e9f61ccd9 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX 8
+#define VIRT_CPUS_MAX 32
#define VIRT_SOCKETS_MAX 8
#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
--
2.31.1
next prev parent reply other threads:[~2022-01-05 22:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-05 21:39 [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis
2022-01-05 21:39 ` [PATCH v4 1/8] hw/intc: sifive_plic: Add a reset function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 2/8] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2022-01-05 21:39 ` [PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2022-01-05 21:39 ` [PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2022-01-05 21:39 ` [PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2022-01-05 21:39 ` [PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2022-01-05 21:39 ` Alistair Francis [this message]
2022-01-05 22:28 ` [PATCH v4 0/8] A collection of RISC-V cleanups and improvements Alistair Francis
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