From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 24/37] target/riscv: moving some insns close to similar insns
Date: Sat, 8 Jan 2022 15:50:35 +1000 [thread overview]
Message-ID: <20220108055048.3512645-25-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220108055048.3512645-1-alistair.francis@opensource.wdc.com>
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-9-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 51607b3d40..710f5e6a85 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -176,6 +176,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUQ);
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUQ);
-}
-
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64BIT(ctx);
@@ -317,11 +317,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
}
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_logic(ctx, a, tcg_gen_xor_tl);
-}
-
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
@@ -332,6 +327,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
}
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_logic(ctx, a, tcg_gen_xor_tl);
+}
+
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_logic(ctx, a, tcg_gen_or_tl);
--
2.31.1
next prev parent reply other threads:[~2022-01-08 7:09 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 5:50 [PULL 00/37] riscv-to-apply queue Alistair Francis
2022-01-08 5:50 ` [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs Alistair Francis
2022-01-08 5:50 ` [PULL 02/37] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Alistair Francis
2022-01-08 5:50 ` [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Alistair Francis
2022-01-08 5:50 ` [PULL 04/37] hw/intc: sifive_plic: Add a reset function Alistair Francis
2022-01-08 5:50 ` [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2022-01-08 5:50 ` [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2022-01-08 5:50 ` [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2022-01-08 5:50 ` [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2022-01-08 5:50 ` [PULL 09/37] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2022-01-08 5:50 ` [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2022-01-08 5:50 ` [PULL 11/37] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2022-01-08 5:50 ` [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0 Alistair Francis
2022-01-08 5:50 ` [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns Alistair Francis
2022-01-08 5:50 ` [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns Alistair Francis
2022-01-08 5:50 ` [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing " Alistair Francis
2022-01-08 5:50 ` [PULL 16/37] target/riscv: Fix position of 'experimental' comment Alistair Francis
2022-01-08 5:50 ` [PULL 17/37] exec/memop: Adding signedness to quad definitions Alistair Francis
2022-01-08 5:50 ` [PULL 18/37] exec/memop: Adding signed quad and octo defines Alistair Francis
2022-01-08 5:50 ` [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations Alistair Francis
2022-01-08 5:50 ` [PULL 20/37] target/riscv: additional macros to check instruction support Alistair Francis
2022-01-08 5:50 ` [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers Alistair Francis
2022-01-08 5:50 ` [PULL 22/37] target/riscv: array for the 64 upper bits of 128-bit registers Alistair Francis
2022-01-08 5:50 ` [PULL 23/37] target/riscv: setup everything for rv64 to support rv128 execution Alistair Francis
2022-01-08 5:50 ` Alistair Francis [this message]
2022-01-08 5:50 ` [PULL 25/37] target/riscv: accessors to registers upper part and 128-bit load/store Alistair Francis
2022-01-08 5:50 ` [PULL 26/37] target/riscv: support for 128-bit bitwise instructions Alistair Francis
2022-01-08 5:50 ` [PULL 27/37] target/riscv: support for 128-bit U-type instructions Alistair Francis
2022-01-08 5:50 ` [PULL 28/37] target/riscv: support for 128-bit shift instructions Alistair Francis
2022-01-08 5:50 ` [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions Alistair Francis
2022-01-08 5:50 ` [PULL 30/37] target/riscv: support for 128-bit M extension Alistair Francis
2022-01-08 5:50 ` [PULL 31/37] target/riscv: adding high part of some csrs Alistair Francis
2022-01-08 5:50 ` [PULL 32/37] target/riscv: helper functions to wrap calls to 128-bit csr insns Alistair Francis
2022-01-08 5:50 ` [PULL 33/37] target/riscv: modification of the trans_csrxx for 128-bit support Alistair Francis
2022-01-08 5:50 ` [PULL 34/37] target/riscv: actual functions to realize crs 128-bit insns Alistair Francis
2022-01-08 5:50 ` [PULL 35/37] target/riscv: Set the opcode in DisasContext Alistair Francis
2022-01-08 5:50 ` [PULL 36/37] target/riscv: Fixup setting GVA Alistair Francis
2022-01-08 5:50 ` [PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2022-01-08 17:37 ` [PULL 00/37] riscv-to-apply queue Richard Henderson
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