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envelope-from=prvs=000118587=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jim Shu Real PDMA supports high 32-bit read/write memory access of 64-bit register. The following result is PDMA tested in U-Boot on Unmatched board: 1. Real PDMA allows high 32-bit read/write to 64-bit register. =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0 =3D> mw.l 0x3000000 0x1 <=3D Claim channel 0 =3D> mw.l 0x3000010 0x80000000 <=3D Write low 32-bit NextDe= st (NextDest =3D 0x280000000) =3D> mw.l 0x3000014 0x2 <=3D Write high 32-bit NextD= est =3D> md.l 0x3000010 1 <=3D Dump low 32-bit NextDes= t 03000010: 80000000 =3D> md.l 0x3000014 1 <=3D Dump high 32-bit NextDe= st 03000014: 00000002 =3D> mw.l 0x3000018 0x80001000 <=3D Write low 32-bit NextSr= c (NextSrc =3D 0x280001000) =3D> mw.l 0x300001c 0x2 <=3D Write high 32-bit NextS= rc =3D> md.l 0x3000018 1 <=3D Dump low 32-bit NextSrc 03000010: 80001000 =3D> md.l 0x300001c 1 <=3D Dump high 32-bit NextSr= c 03000014: 00000002 2. PDMA transfer from 0x280001000 to 0x280000000 is OK. =3D> mw.q 0x3000008 0x4 <=3D NextBytes =3D 4 =3D> mw.l 0x3000004 0x22000000 <=3D wsize =3D rsize =3D 2 (= 2^2 =3D 4 bytes) =3D> mw.l 0x280000000 0x87654321 <=3D Fill test data to dst =3D> mw.l 0x280001000 0x12345678 <=3D Fill test data to src =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory con= tents 280000000: 87654321 !Ce. 280001000: 12345678 xV4. =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 00000001 22000000 00000004 00000000 ......."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> mw.l 0x3000000 0x3 <=3D Set channel 0 run and c= laim bits =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 40000001 22000000 00000004 00000000 ...@..."........ 03000010: 80000000 00000002 80001000 00000002 ................ =3D> md.l 0x280000000 1; md.l 0x280001000 1 <=3D Dump src/dst memory con= tents 280000000: 12345678 xV4. 280001000: 12345678 xV4. Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20220104063408.658169-2-jim.shu@sifive.com Signed-off-by: Alistair Francis --- hw/dma/sifive_pdma.c | 177 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 155 insertions(+), 22 deletions(-) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 85fe34f5f3..f4df16449b 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -177,18 +177,44 @@ static inline void sifive_pdma_update_irq(SiFivePDM= AState *s, int ch) s->chan[ch].state =3D DMA_CHAN_STATE_IDLE; } =20 -static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned s= ize) +static uint64_t sifive_pdma_readq(SiFivePDMAState *s, int ch, hwaddr off= set) { - SiFivePDMAState *s =3D opaque; - int ch =3D SIFIVE_PDMA_CHAN_NO(offset); uint64_t val =3D 0; =20 - if (ch >=3D SIFIVE_PDMA_CHANS) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", - __func__, ch); - return 0; + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + val =3D s->chan[ch].next_bytes; + break; + case DMA_NEXT_DST: + val =3D s->chan[ch].next_dst; + break; + case DMA_NEXT_SRC: + val =3D s->chan[ch].next_src; + break; + case DMA_EXEC_BYTES: + val =3D s->chan[ch].exec_bytes; + break; + case DMA_EXEC_DST: + val =3D s->chan[ch].exec_dst; + break; + case DMA_EXEC_SRC: + val =3D s->chan[ch].exec_src; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX = "\n", + __func__, offset); + break; } =20 + return val; +} + +static uint32_t sifive_pdma_readl(SiFivePDMAState *s, int ch, hwaddr off= set) +{ + uint32_t val =3D 0; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -198,28 +224,47 @@ static uint64_t sifive_pdma_read(void *opaque, hwad= dr offset, unsigned size) val =3D s->chan[ch].next_config; break; case DMA_NEXT_BYTES: - val =3D s->chan[ch].next_bytes; + val =3D extract64(s->chan[ch].next_bytes, 0, 32); + break; + case DMA_NEXT_BYTES + 4: + val =3D extract64(s->chan[ch].next_bytes, 32, 32); break; case DMA_NEXT_DST: - val =3D s->chan[ch].next_dst; + val =3D extract64(s->chan[ch].next_dst, 0, 32); + break; + case DMA_NEXT_DST + 4: + val =3D extract64(s->chan[ch].next_dst, 32, 32); break; case DMA_NEXT_SRC: - val =3D s->chan[ch].next_src; + val =3D extract64(s->chan[ch].next_src, 0, 32); + break; + case DMA_NEXT_SRC + 4: + val =3D extract64(s->chan[ch].next_src, 32, 32); break; case DMA_EXEC_CONFIG: val =3D s->chan[ch].exec_config; break; case DMA_EXEC_BYTES: - val =3D s->chan[ch].exec_bytes; + val =3D extract64(s->chan[ch].exec_bytes, 0, 32); + break; + case DMA_EXEC_BYTES + 4: + val =3D extract64(s->chan[ch].exec_bytes, 32, 32); break; case DMA_EXEC_DST: - val =3D s->chan[ch].exec_dst; + val =3D extract64(s->chan[ch].exec_dst, 0, 32); + break; + case DMA_EXEC_DST + 4: + val =3D extract64(s->chan[ch].exec_dst, 32, 32); break; case DMA_EXEC_SRC: - val =3D s->chan[ch].exec_src; + val =3D extract64(s->chan[ch].exec_src, 0, 32); + break; + case DMA_EXEC_SRC + 4: + val =3D extract64(s->chan[ch].exec_src, 32, 32); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX = "\n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX = "\n", __func__, offset); break; } @@ -227,19 +272,66 @@ static uint64_t sifive_pdma_read(void *opaque, hwad= dr offset, unsigned size) return val; } =20 -static void sifive_pdma_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned s= ize) { SiFivePDMAState *s =3D opaque; int ch =3D SIFIVE_PDMA_CHAN_NO(offset); - bool claimed, run; + uint64_t val =3D 0; =20 if (ch >=3D SIFIVE_PDMA_CHANS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", __func__, ch); - return; + return 0; + } + + switch (size) { + case 8: + val =3D sifive_pdma_readq(s, ch, offset); + break; + case 4: + val =3D sifive_pdma_readl(s, ch, offset); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid read size %u to PDMA= \n", + __func__, size); + return 0; } =20 + return val; +} + +static void sifive_pdma_writeq(SiFivePDMAState *s, int ch, + hwaddr offset, uint64_t value) +{ + offset &=3D 0xfff; + switch (offset) { + case DMA_NEXT_BYTES: + s->chan[ch].next_bytes =3D value; + break; + case DMA_NEXT_DST: + s->chan[ch].next_dst =3D value; + break; + case DMA_NEXT_SRC: + s->chan[ch].next_src =3D value; + break; + case DMA_EXEC_BYTES: + case DMA_EXEC_DST: + case DMA_EXEC_SRC: + /* these are read-only registers */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX = "\n", + __func__, offset); + break; + } +} + +static void sifive_pdma_writel(SiFivePDMAState *s, int ch, + hwaddr offset, uint32_t value) +{ + bool claimed, run; + offset &=3D 0xfff; switch (offset) { case DMA_CONTROL: @@ -282,27 +374,68 @@ static void sifive_pdma_write(void *opaque, hwaddr = offset, s->chan[ch].next_config =3D value; break; case DMA_NEXT_BYTES: - s->chan[ch].next_bytes =3D value; + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 0, 32, value); + break; + case DMA_NEXT_BYTES + 4: + s->chan[ch].next_bytes =3D + deposit64(s->chan[ch].next_bytes, 32, 32, value); break; case DMA_NEXT_DST: - s->chan[ch].next_dst =3D value; + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 0, 32, = value); + break; + case DMA_NEXT_DST + 4: + s->chan[ch].next_dst =3D deposit64(s->chan[ch].next_dst, 32, 32,= value); break; case DMA_NEXT_SRC: - s->chan[ch].next_src =3D value; + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 0, 32, = value); + break; + case DMA_NEXT_SRC + 4: + s->chan[ch].next_src =3D deposit64(s->chan[ch].next_src, 32, 32,= value); break; case DMA_EXEC_CONFIG: case DMA_EXEC_BYTES: + case DMA_EXEC_BYTES + 4: case DMA_EXEC_DST: + case DMA_EXEC_DST + 4: case DMA_EXEC_SRC: + case DMA_EXEC_SRC + 4: /* these are read-only registers */ break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX = "\n", + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX = "\n", __func__, offset); break; } } =20 +static void sifive_pdma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + SiFivePDMAState *s =3D opaque; + int ch =3D SIFIVE_PDMA_CHAN_NO(offset); + + if (ch >=3D SIFIVE_PDMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, ch); + return; + } + + switch (size) { + case 8: + sifive_pdma_writeq(s, ch, offset, value); + break; + case 4: + sifive_pdma_writel(s, ch, offset, (uint32_t) value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid write size %u to PDM= A\n", + __func__, size); + break; + } +} + static const MemoryRegionOps sifive_pdma_ops =3D { .read =3D sifive_pdma_read, .write =3D sifive_pdma_write, --=20 2.31.1