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envelope-from=prvs=000118587=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis In preparation for adding support for the illegal instruction address let's fixup the Hypervisor extension setting GVA logic and improve the variable names. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com --- target/riscv/cpu_helper.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 10f3baba53..ddacb8533a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -998,6 +998,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + bool write_gva =3D false; uint64_t s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wi= de @@ -1006,7 +1007,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg =3D async ? env->mideleg : env->medeleg; - bool write_tval =3D false; target_ulong tval =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; @@ -1035,7 +1035,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: - write_tval =3D true; + write_gva =3D true; tval =3D env->badaddr; break; default: @@ -1072,18 +1072,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (env->two_stage_lookup && write_tval) { - /* - * If we are writing a guest virtual address to stval, s= et - * this to 1. If we are trapping to VS we will set this = to 0 - * later. - */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 1)= ; - } else { - /* For other HS-mode traps, we set this to 0. */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0)= ; - } - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) = { /* Trap to VS mode */ /* @@ -1094,7 +1082,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D=3D IRQ_VS_EXT) { cause =3D cause - 1; } - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, 0)= ; + write_gva =3D false; } else if (riscv_cpu_virt_enabled(env)) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); @@ -1103,6 +1091,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); =20 + htval =3D env->guest_phys_fault_addr; =20 riscv_cpu_set_virt_enabled(env, 0); @@ -1110,7 +1099,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trap into HS mode */ env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fa= lse); htval =3D env->guest_phys_fault_addr; + write_gva =3D false; } + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, write_= gva); } =20 s =3D env->mstatus; --=20 2.31.1