From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function
Date: Sat, 8 Jan 2022 15:50:17 +1000 [thread overview]
Message-ID: <20220108055048.3512645-7-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220108055048.3512645-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-4-alistair.francis@opensource.wdc.com>
---
hw/intc/sifive_plic.c | 55 +++++++++----------------------------------
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 698492ce77..44d24b3c59 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -199,70 +199,37 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
{
SiFivePLICState *plic = opaque;
- /* writes must be 4 byte words */
- if ((addr & 0x3) != 0) {
- goto err;
- }
-
- if (addr >= plic->priority_base && /* 4 bytes per source */
- addr < plic->priority_base + (plic->num_sources << 2))
- {
+ if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read priority: irq=%d priority=%d\n",
- irq, plic->source_priority[irq]);
- }
+
return plic->source_priority[irq];
- } else if (addr >= plic->pending_base && /* 1 bit per source */
- addr < plic->pending_base + (plic->num_sources >> 3))
- {
+ } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
uint32_t word = (addr - plic->pending_base) >> 2;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read pending: word=%d value=%d\n",
- word, plic->pending[word]);
- }
+
return plic->pending[word];
- } else if (addr >= plic->enable_base && /* 1 bit per source */
- addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
- {
+ } else if (addr_between(addr, plic->enable_base,
+ plic->num_addrs * plic->enable_stride)) {
uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
+
if (wordid < plic->bitfield_words) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode), wordid,
- plic->enable[addrid * plic->bitfield_words + wordid]);
- }
return plic->enable[addrid * plic->bitfield_words + wordid];
}
- } else if (addr >= plic->context_base && /* 1 bit per source */
- addr < plic->context_base + plic->num_addrs * plic->context_stride)
- {
+ } else if (addr_between(addr, plic->context_base,
+ plic->num_addrs * plic->context_stride)) {
uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
uint32_t contextid = (addr & (plic->context_stride - 1));
+
if (contextid == 0) {
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read priority: hart%d-%c priority=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- plic->target_priority[addrid]);
- }
return plic->target_priority[addrid];
} else if (contextid == 4) {
uint32_t value = sifive_plic_claim(plic, addrid);
- if (RISCV_DEBUG_PLIC) {
- qemu_log("plic: read claim: hart%d-%c irq=%x\n",
- plic->addr_config[addrid].hartid,
- mode_to_char(plic->addr_config[addrid].mode),
- value);
- }
+
sifive_plic_update(plic);
return value;
}
}
-err:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid register read 0x%" HWADDR_PRIx "\n",
__func__, addr);
--
2.31.1
next prev parent reply other threads:[~2022-01-08 6:18 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 5:50 [PULL 00/37] riscv-to-apply queue Alistair Francis
2022-01-08 5:50 ` [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs Alistair Francis
2022-01-08 5:50 ` [PULL 02/37] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register Alistair Francis
2022-01-08 5:50 ` [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers Alistair Francis
2022-01-08 5:50 ` [PULL 04/37] hw/intc: sifive_plic: Add a reset function Alistair Francis
2022-01-08 5:50 ` [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2022-01-08 5:50 ` Alistair Francis [this message]
2022-01-08 5:50 ` [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2022-01-08 5:50 ` [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2022-01-08 5:50 ` [PULL 09/37] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2022-01-08 5:50 ` [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2022-01-08 5:50 ` [PULL 11/37] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2022-01-08 5:50 ` [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0 Alistair Francis
2022-01-08 5:50 ` [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns Alistair Francis
2022-01-08 5:50 ` [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns Alistair Francis
2022-01-08 5:50 ` [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing " Alistair Francis
2022-01-08 5:50 ` [PULL 16/37] target/riscv: Fix position of 'experimental' comment Alistair Francis
2022-01-08 5:50 ` [PULL 17/37] exec/memop: Adding signedness to quad definitions Alistair Francis
2022-01-08 5:50 ` [PULL 18/37] exec/memop: Adding signed quad and octo defines Alistair Francis
2022-01-08 5:50 ` [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations Alistair Francis
2022-01-08 5:50 ` [PULL 20/37] target/riscv: additional macros to check instruction support Alistair Francis
2022-01-08 5:50 ` [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers Alistair Francis
2022-01-08 5:50 ` [PULL 22/37] target/riscv: array for the 64 upper bits of 128-bit registers Alistair Francis
2022-01-08 5:50 ` [PULL 23/37] target/riscv: setup everything for rv64 to support rv128 execution Alistair Francis
2022-01-08 5:50 ` [PULL 24/37] target/riscv: moving some insns close to similar insns Alistair Francis
2022-01-08 5:50 ` [PULL 25/37] target/riscv: accessors to registers upper part and 128-bit load/store Alistair Francis
2022-01-08 5:50 ` [PULL 26/37] target/riscv: support for 128-bit bitwise instructions Alistair Francis
2022-01-08 5:50 ` [PULL 27/37] target/riscv: support for 128-bit U-type instructions Alistair Francis
2022-01-08 5:50 ` [PULL 28/37] target/riscv: support for 128-bit shift instructions Alistair Francis
2022-01-08 5:50 ` [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions Alistair Francis
2022-01-08 5:50 ` [PULL 30/37] target/riscv: support for 128-bit M extension Alistair Francis
2022-01-08 5:50 ` [PULL 31/37] target/riscv: adding high part of some csrs Alistair Francis
2022-01-08 5:50 ` [PULL 32/37] target/riscv: helper functions to wrap calls to 128-bit csr insns Alistair Francis
2022-01-08 5:50 ` [PULL 33/37] target/riscv: modification of the trans_csrxx for 128-bit support Alistair Francis
2022-01-08 5:50 ` [PULL 34/37] target/riscv: actual functions to realize crs 128-bit insns Alistair Francis
2022-01-08 5:50 ` [PULL 35/37] target/riscv: Set the opcode in DisasContext Alistair Francis
2022-01-08 5:50 ` [PULL 36/37] target/riscv: Fixup setting GVA Alistair Francis
2022-01-08 5:50 ` [PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2022-01-08 17:37 ` [PULL 00/37] riscv-to-apply queue Richard Henderson
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