From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org
Subject: [PATCH v4 08/12] tcg/mips: Split out tcg_out_movi_two
Date: Fri, 7 Jan 2022 22:36:40 -0800 [thread overview]
Message-ID: <20220108063644.478043-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220108063644.478043-1-richard.henderson@linaro.org>
Emit all 32-bit signed constants, which can be loaded in two insns.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 35 ++++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 8741fdd49c..142583b613 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -541,6 +541,22 @@ static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
return false;
}
+static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
+{
+ /*
+ * All signed 32-bit constants are loadable with two immediates,
+ * and everything else requires more work.
+ */
+ if (arg == (int32_t)arg) {
+ if (!tcg_out_movi_one(s, ret, arg)) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
+ return true;
+ }
+ return false;
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
@@ -548,21 +564,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
arg = (int32_t)arg;
}
- if (tcg_out_movi_one(s, ret, arg)) {
+ /* Load all 32-bit constants. */
+ if (tcg_out_movi_two(s, ret, arg)) {
return;
}
- if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
- tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
} else {
- tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
- if (arg & 0xffff0000ull) {
- tcg_out_dsll(s, ret, ret, 16);
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
- tcg_out_dsll(s, ret, ret, 16);
- } else {
- tcg_out_dsll(s, ret, ret, 32);
- }
+ tcg_out_dsll(s, ret, ret, 32);
}
if (arg & 0xffff) {
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
--
2.25.1
next prev parent reply other threads:[~2022-01-08 8:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-08 6:36 [PATCH v4 00/12] tcg/mips: Unaligned access and other cleanup Richard Henderson
2022-01-08 6:36 ` [PATCH v4 01/12] tcg/mips: Support unaligned access for user-only Richard Henderson
2022-01-08 6:36 ` [PATCH v4 02/12] tcg/mips: Support unaligned access for softmmu Richard Henderson
2022-01-08 6:36 ` [PATCH v4 03/12] tcg/mips: Move TCG_AREG0 to S8 Richard Henderson
2022-01-08 6:36 ` [PATCH v4 04/12] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Richard Henderson
2022-01-08 6:36 ` [PATCH v4 05/12] tcg/mips: Unify TCG_GUEST_BASE_REG tests Richard Henderson
2022-01-08 9:20 ` Philippe Mathieu-Daudé
2022-01-08 6:36 ` [PATCH v4 06/12] tcg/mips: Create and use TCG_REG_TB Richard Henderson
2022-01-08 6:36 ` [PATCH v4 07/12] tcg/mips: Split out tcg_out_movi_one Richard Henderson
2022-01-08 6:36 ` Richard Henderson [this message]
2022-01-08 6:36 ` [PATCH v4 09/12] tcg/mips: Use the constant pool for 64-bit constants Richard Henderson
2022-01-08 6:36 ` [PATCH v4 10/12] tcg/mips: Aggressively use the constant pool for n64 calls Richard Henderson
2022-01-08 6:36 ` [PATCH v4 11/12] tcg/mips: Try tb-relative addresses in tcg_out_movi Richard Henderson
2022-01-08 6:36 ` [PATCH v4 12/12] tcg/mips: Try three insns with shift and add " Richard Henderson
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